IP Library › Granted Patent US 9,323,660
Granted Patent B2
US 9,323,660 · App. 13/684,823 · Granted Apr 26, 2016

Memory access control apparatus and memory access control method

Inventor: Yuko Tamagawa (Osaka, JP)
Assignee: MegaChips Corporation
G06F12/0246G06F3/06G06F3/0604G06F12/00G11C16/3427
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,323,660
App. No.
13/684,823
Granted
Apr 26, 2016
Kind
B2
Abstract

A memory is readable by page and erasable by block including a plurality of pages. After a read request to the memory is issued, a memory controller specifies all blocks which can be accessed based on an address specified by a read command, as candidate blocks, and specifies an inspection target page out of pages included in the candidate blocks on the basis of a predetermined rule. The memory controller inspects whether or not there is an error in the inspection target page.

Claims (47)

1. A memory access control apparatus for controlling access to a rewritable nonvolatile semiconductor memory which is readable by page and erasable by block including a plurality of pages, comprising:

a read count memory configured to store a read count for said nonvolatile semiconductor memory by block;

a specifying part configured to specify an inspection target page after a read request to said nonvolatile semiconductor memory is issued; and

an inspection part configured to inspect whether there is an error in said inspection target page,

wherein said specifying part includes:

a candidate specifying part configured to specify all blocks which can be accessed based on an address specified by a read command, as candidate blocks;

a block specifying part configured to specify a block whose read count is the highest among said candidate blocks as an inspection target block by referring to said read count memory; and

a page specifying part configured to specify said inspection target page out of said inspection target block on the basis of a predetermined rule.

2. The memory access control apparatus according to claim 1 , further comprising:

a pointer memory part configured to store a pointer for specifying said inspection target page in each block,

wherein said page specifying part specifies said inspection target page in said inspection target block from a pointer for said inspection target block by referring to said pointer memory part.

3. The memory access control apparatus according to claim 2 , wherein

after said specifying part specifies said inspection target page, said pointer for a corresponding block is incremented by one page.

4. The memory access control apparatus according to claim 3 , wherein

after the last page in said corresponding block is specified as an inspection target, said pointer is updated so that the first page in said corresponding block is next specified as an inspection target.

5. The memory access control apparatus according to claim 4 , wherein

said pointer for said corresponding block is reset to an initial position after all pages in said corresponding block are specified as said inspection target page by said specifying part.

6. The memory access control apparatus according to claim 4 , wherein

a read count for said inspection target block is reset to zero after all pages in said block are specified as said inspection target page by said specifying part.

7. The memory access control apparatus according to claim 1 , wherein

said specifying part specifies said inspection target page prior to execution of a read operation on said nonvolatile semiconductor memory.

8. The memory access control apparatus according to claim 1 , wherein

said specifying part specifies said inspection target page after completion of a read operation on said nonvolatile semiconductor memory and prior to execution of a next read operation.

9. The memory access control apparatus according to claim 1 , wherein

the maximum number of pages for each read operation is determined in advance with respect to said nonvolatile semiconductor memory, and

said candidate specifying part specifies all blocks which can be accessed on the basis of an address specified in a read operation and said maximum number of pages.

10. The memory access control apparatus according to claim 1 , wherein

said read count memory counts up said read count from the time when said memory access control apparatus is powered on.

11. A memory access control method for controlling access to a rewritable nonvolatile semiconductor memory which is readable by page and erasable by block including a plurality of pages, comprising:

(a) storing a read count for said nonvolatile semiconductor memory by block;

(b) specifying an inspection target page after a read request to said nonvolatile semiconductor memory is issued; and

(c) inspecting whether there is an error in said inspection target page,

wherein the step (b) includes:

specifying all blocks which can be accessed based on an address specified by a read command, as candidate blocks;

specifying a block whose read count is the highest among said candidate blocks as an inspection target block by referring to a read count stored in the step (a); and

specifying said inspection target page out of said inspection target block on the basis of a predetermined rule.

12. The memory access control method according to claim 11 , further comprising:

(d) storing a pointer for specifying said inspection target page in each block,

wherein the step of specifying said inspection target page out of said inspection target block includes specifying said inspection target page in said inspection target block from a pointer for said inspection target block by referring to a pointer stored in the step (d).

13. A memory access control apparatus for controlling access to a rewritable nonvolatile semiconductor memory which is readable by page and erasable by block including a plurality of pages, comprising:

a read count memory configured to store a read count for said nonvolatile semiconductor memory by block; and

circuitry configured to:

specify an inspection target page after a read request to said nonvolatile semiconductor memory is issued;

inspect whether there is an error in said inspection target page;

specify all blocks which can be accessed based on an address specified by a read command, as candidate blocks;

specify a block whose read count is the highest among said candidate blocks as an inspection target block by referring to said read count memory; and

specify said inspection target page out of said inspection target block on the basis of a predetermined rule.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2012
From: TAMAGAWA, YUKO
To: MEGACHIPS CORPORATION
Reel/Frame 029348/0569 →
Priority Claims (1)
JP 2011-264723 · Dec 2, 2011 · national
Continuity (1)
Related Publication 20130145082A1 · Jun 6, 2013