ANALYSIS OF STIMULUS BY RFID
The present invention is directed to a process for manufacturing a capacitor for an RFID device. The process utilizes stencils to spray-coat capacitor electrodes about a substrate, and in other embodiments, the process spray coats a first capacitor on a substrate, then an insulator on the first capacitor, and then a second capacitor on the insulator.
1 . A process for manufacturing a capacitor for an RFID device, said process comprising:
positioning a first electrode stencil, proximate to an RFID substrate, having a first electrode void with a substantially two-dimensional representation of a predetermined capacitor first electrode area;
spray-coating at least one first electrode layer on said substrate through said first electrode void to form a first electrode;
locating an insulator stencil, proximate to said RFID substrate, having an insulator void with a substantially two-dimensional representation of a predetermined capacitor insulator area;
spray-coating an insulator layer on said first electrode through said insulator void;
applying a second electrode stencil, proximate to said RFID substrate, having a second electrode void with a substantially two-dimensional representation of a predetermined capacitor second electrode area; and
spray-coating at least one second electrode layer on said insulator layer through said second electrode void to form a second electrode.
2 . The process of claim 1 wherein said positioning step includes positioning said first electrode stencil having a first electrode void with said substantially two-dimensional representation of said predetermined capacitor first electrode area and a first capacitor lead.
3 . The process of claim 2 wherein said applying step includes applying said second electrode stencil having said second electrode void with said substantially two-dimensional representation of said predetermined capacitor second electrode area and a second capacitor lead.
4 . The process of claim 1 wherein said applying step includes applying said second electrode stencil having said second electrode void with a substantially two-dimensional representation of said predetermined capacitor second electrode area and a second capacitor lead.
5 . The process of claim 4 wherein said positioning step includes positioning said first electrode stencil having said first electrode void with said substantially two-dimensional representation of said predetermined capacitor first electrode area and a first capacitor lead.
6 . A process for manufacturing a capacitor for an RFID device, said process comprising:
positioning a first electrode stencil, proximate to an RFID substrate, having a first electrode void with a substantially two-dimensional representation of a predetermined capacitor first electrode area;
spray-coating at least one first electrode layer on said substrate through said void to form a first electrode;
applying a second electrode stencil, proximate to said RFID substrate, having a second electrode void with a substantially two-dimensional representation of a predetermined capacitor second electrode area; and
spray-coating at least one second electrode layer on said insulator layer through said second electrode void, concentric with and opposite of said first electrode, to form a second electrode.
7 . The process of claim 6 wherein said positioning step includes positioning said first electrode stencil having a first electrode void with said substantially two-dimensional representation of said predetermined capacitor first electrode area and a first capacitor lead.
8 . The process of claim 7 wherein said applying step includes applying said second electrode stencil having said second electrode void with said substantially two-dimensional representation of said predetermined capacitor second electrode area and a second capacitor lead.
9 . The process of claim 6 wherein said applying step includes applying said second electrode stencil having said second electrode void with a substantially two-dimensional representation of said predetermined capacitor second electrode area and a second capacitor lead.
10 . The process of claim 9 wherein said positioning step includes positioning said first electrode stencil having said first electrode void with said substantially two-dimensional representation of said predetermined capacitor first electrode area and a first capacitor lead.