Control circuitry
An arrangement is described in which phase parity or phase opposition between two signals can be determined, and if necessary remedial action may be taken.
1. An operating arrangement for a circuit, the circuit having plural circuit portions, the arrangement comprising a node for a frequency source coupled to plural frequency dividers, each frequency divider having an output connected to provide a respective divided frequency to a respective portion of the circuit, the arrangement comprising phase comparison circuitry connected to the outputs of the frequency dividers and correction circuitry responsive to an output of the phase comparison circuitry to act upon at least one frequency divider to cause the outputs of the frequency dividers to assume a desired phase relationship, wherein each frequency divider is a divide-by-two circuit, there are two divide-by-two circuits and the correction circuitry is operable to cause the outputs of the divide-by-two circuits into phase parity, wherein each divide-by-two circuit provides first and second quadrature outputs and each circuit portion has first and second inputs for quadrature signals, the correction circuitry is operable to select between a first configuration in which the first and second quadrature outputs are connected to the first and second inputs and a second configuration in which the first and second quadrature outputs are connected to the second and first inputs respectively.
2. The arrangement of claim 1 , wherein the phase comparison circuitry is operable to compare one of the first and second quadrature outputs of each divide-by-two circuit.
3. The arrangement of claim 1 , wherein the phase comparison circuitry is operable to compare both of the first and second quadrature outputs of each divide-by-two circuit.
4. The arrangement of claim 1 , wherein the phase comparison circuitry is operable to compare the sums of the first and second quadrature outputs of each divide-by-two circuit.
5. An operating arrangement for a circuit, the circuit having plural circuit portions, the arrangement comprising a node for a frequency source coupled to plural frequency dividers, each frequency divider having an output connected to provide a respective divided frequency to a respective portion of the circuit, the arrangement comprising phase comparison circuitry connected to the outputs of the frequency dividers and correction circuitry responsive to an output of the phase comparison circuitry to act upon at least one frequency divider to cause the outputs of the frequency dividers to assume a desired phase relationship, wherein each frequency divider is a divide-by-two circuit, there are two divide-by-two circuits and the correction circuitry is operable to cause the outputs of the divide-by-two circuits into phase opposition, wherein each divide-by-two circuit provides first and second quadrature outputs and each circuit portion has first and second inputs for quadrature signals, the correction circuitry is operable to select between a first configuration in which the first and second outputs are connected to the first and second inputs and a second configuration in which the first and second outputs are connected to the second and first inputs respectively.
6. The arrangement of claim 5 , wherein the phase comparison circuitry is operable to compare one of the first and second quadrature outputs of each divide-by-two circuit.
7. The arrangement of claim 5 , wherein the phase comparison circuitry is operable to compare both of the first and second quadrature outputs of each divide-by-two circuit.
8. The arrangement of claim 5 , wherein the phase comparison circuitry is operable to compare the sums of the first and second quadrature outputs of each divide-by-two circuit.
9. An operating arrangement for a circuit, the circuit having plural circuit portions, the arrangement comprising a node for a frequency source coupled to plural frequency dividers, each frequency divider having an output connected to provide a respective divided frequency to a respective portion of the circuit, the arrangement comprising phase comparison circuitry connected to the outputs of the frequency dividers and correction circuitry responsive to an output of the phase comparison circuitry to act upon at least one frequency divider to cause the outputs of the frequency dividers to assume a desired phase relationship, further having an input for a sampling signal, the input for the sampling signal being connected to a control node of the phase comparison circuitry.
10. An operating arrangement according to claim 9 , further having an inhibit circuit having an enable input for inhibiting a signal at the output of the correction circuitry from acting upon said at least one frequency divider.
11. A radio transceiver comprising an operating arrangement for the transceiver, the transceiver having plural mixers, the operating arrangement comprising a node for a frequency source coupled to plural two divide-by-two circuits, each divide-by-two circuit operable to provide quadrature outputs to a respective mixer as quadrature local oscillator signals, the operating arrangement comprising phase comparison circuitry connected to the outputs of the divide-by-two circuits and correction circuitry responsive to an output of the phase comparison circuitry to act upon at least one divide-by-two circuit to cause the outputs of the divide-by-two circuits to assume a desired phase relationship.
12. An operating arrangement for a circuit, the circuit having plural circuit portions, the arrangement comprising a node for a frequency source coupled to plural frequency dividers, each frequency divider having an output connected to provide a respective divided frequency to a respective portion of the circuit, the arrangement comprising phase comparison circuitry connected to the outputs of the frequency dividers and correction circuitry responsive to an output of the phase comparison circuitry to act upon at least one frequency divider to cause the outputs of the frequency dividers to assume a desired phase relationship, wherein each frequency divider is a divide-by-two circuit, there are two divide-by-two circuits and the correction circuitry is operable to cause the outputs of the divide-by-two circuits into phase opposition, further having an inhibit circuit having an enable input for inhibiting a signal at the output of the correction circuitry from acting upon said at least one frequency divider.