Data processing apparatus and related methods of debugging processing circuitry
A data processing apparatus having processing circuitry and debug circuitry is debugged by operating the processing circuitry to generate data. The debug circuitry is employed to generate trace elements indicative of the operation of the processing circuitry. Trace elements are caused to be output from the data processing apparatus over a communication bus capable of connecting a plurality of devices. The communication bus is controlled by a protocol for data interchange requiring data interchange from any device on the communication bus to be controlled by a single processing system. The passing of the trace elements onto the communication bus is controlled using an interface unit of the debug circuitry. The interface unit comprises a controller arranged to allow each of the interface unit and processing circuitry to be separate processing systems which can each independently control data interchange from the data processing apparatus.
1. A data processing apparatus, comprising processing circuitry, which in use, generates data, debug circuitry arranged to debug operation of the processing circuitry and an interface unit containing a controller arranged to control operation of the interface unit, wherein each of the processing circuitry and the interface unit constitute a single processing system and wherein
the processing apparatus includes bus circuitry arranged to pass data into and/or out of the processing apparatus over a communication bus capable of connecting a plurality of devices;
wherein the communication bus is controlled by a protocol for data interchange requiring data interchange from any device on the communication bus to be controlled by a single processing system;
the debug circuitry comprises monitoring circuitry arranged to monitor the data generated, in use, by the processing circuitry and generate a stream of trace elements; and
the interface unit being arranged to interface, using the bus circuitry, the trace elements generated by the monitoring circuitry onto the communication bus to be output, in use, from the processing apparatus using the communication bus such that each of the processing circuitry and the interface unit are arranged to independently control data interchange from the data processing apparatus.
2. An apparatus according to claim 1 in which each of the processing circuitry and interface unit appear as separate devices on the communication bus.
3. An apparatus according to claim 1 in which the interface unit is arranged such that it is disconnectable from the bus circuitry and/or communication bus.
4. An apparatus according to claim 3 in which at least a portion of the processing circuitry is arranged to be held in a reset state in order to disconnect the interface from the bus circuitry.
5. An apparatus according to claim 3 in which the interface is arranged such that it can be logically connected and disconnected during operation in a manner that appears to the host and processing circuitry as standard plug/unplug behaviour.
6. An apparatus according to claim 1 in which at least portions of the debug circuitry are interposed between blocks of the bus circuitry.
7. An apparatus according to claim 1 in which the controller is implemented as a state machine.
8. An apparatus according to claim 1 in which the communication bus is a USB bus.
9. An apparatus according to claim 1 in which the interface unit comprises a USB hub.
10. Debug logic, arranged to monitor processing circuitry, wherein the debug logic comprises the following:
monitoring circuitry arranged to perform the monitoring of the processing circuitry and generate a stream of trace elements;
an interface unit arranged to interface the trace elements generated by the monitoring circuitry on to a communication bus capable of connecting a plurality of devices and used by the processing circuitry being monitored wherein the communication bus is controlled by a protocol for data interchange requiring data interchange from any device on the communication bus to be controlled by a single processing system;
wherein the interface unit comprises a controller arranged such that each of the interface unit and the processing circuitry constitute single processing systems, with the debug logic being arranged such that each of the processing circuitry and the interface unit are arranged to independently control data interchange from the data processing apparatus.
11. Logic according to claim 10 which is arranged to be disconnectable from the communication bus to which it interfaces.
12. Logic according to claim 10 which is arranged to have at least portions thereof to be interposed between components of bus circuitry in which the debug logic is implemented.
13. Logic according to claim 10 which is arranged to interface with a USB communication bus.
14. Logic according to claim 13 in which the interface includes a USB hub.
15. Logic according to claim 14 in which the USB hub is arranged to be interposed between a USB MAC block and a USB PHY block.
16. Logic according to claim 10 which is arranged such that the debug circuitry appears as a separate device on the communication bus to the processing circuitry that it is, in use, monitoring.
17. A method of debugging a data processing apparatus having processing circuitry and debug circuitry comprising the following steps of:
operating the processing circuitry to generate data;
employing debug circuitry to generate trace elements indicative of the operation of the processing circuitry;
causing the trace elements to be output from the data processing apparatus over a communication bus capable of connecting a plurality of devices and wherein the communication bus being is controlled by a protocol for data interchange requiring data interchange from any device on the communication bus to be controlled by a single processing system; and
controlling the passing of the trace elements onto the communication bus using an interface unit of the debug circuitry wherein the interface unit comprises a controller arranged to allow each of the interface unit and processing circuitry to be separate processing systems which can each independently control data interchange from the data processing apparatus.
18. A method according to claim 17 in which each of the processing circuitry and the debug circuitry appear as separate devices on the communication bus.
19. A non-transitory machine readable medium containing executable instructions which when read onto a machine cause that machine to perform a method of debugging a data processing apparatus having processing circuitry and debug circuitry comprising:
operating the processing circuitry to generate data;
employing debug circuitry to generate trace elements indicative of the operation of the processing circuitry;
causing the trace elements to be output from a data processing apparatus over a communication bus capable of connecting a plurality of devices and wherein the communication bus being is controlled by a protocol for data interchange requiring data interchange from any device on the communication bus to be controlled by a single processing system; and
controlling the passing of the trace elements onto the communication bus using an interface unit of the debug circuitry wherein the interface unit comprises a controller arranged to allow each of the interface unit and processing circuitry to be separate processing systems which can each independently control data interchange from the data processing apparatus.
20. A machine readable medium according to claim 19 in which each of the processing circuitry and the debug circuitry appear as separate devices on the communication bus.