IP Library Assignment 054736/0771
Patent Assignment
Reel/Frame 054736/0771

Assignment of Assignor's Interest

Recorded: 2020-12-23 Pages: 6
Assignor
ULTRASOC TECHNOLOGIES LTD.
Executed: 2020-11-30
Assignee
MENTOR GRAPHICS CORPORATION
8005 S.W. BOECKMAN RD., WILSONVILLE, OREGON, 97070
Covered Properties (36)
Method of Debugging Multiple Processes
Patent: 8,112,677 →
Application: 12/713,880 →
Publication: US 2011/0214023
Data Processing Apparatus and Related Methods of Debugging Processing Circuitry
Patent: 8,826,081 →
Application: 13/690,923 →
Publication: US 2013/0111274
Prioritising Event Data Over Configuration Data in a Single Interface in a Soc/Debug Architecture
Patent: 9,032,109 →
Application: 13/938,046 →
Publication: US 2014/0013011
Debug Architecture
Patent: 9,218,258 →
Application: 13/938,053 →
Publication: US 2014/0013157
Debug Architecture
Patent: 9,003,232 →
Application: 13/938,065 →
Publication: US 2014/0013161
Debug Architecture
Patent: 9,176,552 →
Application: 13/938,077 →
Publication: US 2014/0013145
Prioritizing Transport of Debug Data on an Integrated Circuit Chip by Data Type
Patent: 9,026,871 →
Application: 13/938,088 →
Publication: US 2014/0013172
Debug Architecture
Patent: 9,703,944 →
Application: 13/938,098 →
Publication: US 2014/0013421
Functional Testing of an Integrated Circuit Chip
Patent: 9,188,638 →
Application: 14/251,044 →
Publication: US 2015/0226801
Monitoring Functional Testing of an Integrated Circuit Chip
Patent: 9,140,753 →
Application: 14/251,157 →
Publication: US 2015/0226795
Routing Debug Messages
Patent: 9,424,166 →
Application: 14/251,260 →
Publication: US 2015/0268302
Debug Architecture
Application: 14/843,745 →
Publication: US 2015/0377965
Functional Testing of an Integrated Circuit Chip
Patent: 9,632,138 →
Application: 14/879,597 →
Publication: US 2016/0033575
Debug Adapter
Application: 15/235,308 →
Publication: US 2017/0045583
Reconfiguring Debug Circuitry
Patent: 9,970,985 →
Application: 15/235,597 →
Publication: US 2017/0045584
Profiling Transactions on an Integrated Circuit Chip
Application: 15/235,647 →
Publication: US 2017/0046288
Tracing Interconnect Circuitry
Application: 15/241,471 →
Publication: US 2017/0052868
Debug Architecture
Patent: 9,927,486 →
Application: 15/241,805 →
Publication: US 2016/0356841
Packet Data Protocol
Application: 15/245,541 →
Publication: US 2017/0063570
Integrated Circuit Security
Application: 15/365,686 →
Publication: US 2017/0153988
Debug Architecture
Patent: 9,928,361 →
Application: 15/617,953 →
Publication: US 2017/0277883
Reconfiguring Debug Circuitry
Application: 15/906,730 →
Publication: US 2018/0188323
Monitoring Accesses to a Region of an Integrated Circuit Chip
Application: 16/292,530 →
Publication: US 2019/0277912
Performance Profiling for a Multithreaded Processor
Application: 16/380,439 →
Publication: US 2020/0326975
Packet Data Protocol
Application: 16/413,829 →
Publication: US 2019/0273631
Variable Address Length Communication Protocol
Application: 16/460,448 →
Publication: US 2020/0015151
Reconfiguring Monitoring Circuitry
Application: 16/525,989 →
Publication: US 2019/0353705
Error Detection Within An Integrated Circuit Chip
Application: 16/528,394 →
Publication: US 2020/0089562
Monitoring Processors Operating in Lockstep
Application: 16/696,812 →
Publication: US 2021/0157667
Generation of Trace Messages Including an Instruction Retirement Count and a Stall Count
Application: 16/850,100 →
Publication: US 2020/0334128
Handling Trace Data for Jumps in Program Flow
Application: 16/925,445 →
Publication: US 2021/0011833
Emulating Broadcast in a Network on Chip
Application: 16/940,960 →
Publication: US 2021/0036880
Routing Messages in an Integrated Circuit Chip Device Using a Crosslinked Tree Structure
Application: 16/994,030 →
Publication: US 2021/0051095
Reconfiguring an Addressing Mechanism for a System on Chip to Bypass a Defective Branch Unit
Application: 16/994,373 →
Publication: US 2021/0049081
Broadcasting Event Messages in a System on Chip Using a Crosslinked Tree Structure
Application: 16/994,444 →
Publication: US 2021/0049055
Message Monitoring
Application: 17/064,594 →
Publication: US 2021/0103537
Related Assignments (20)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest May 11, 2010
From: BARLOW, STEPHEN JOHN; BOWER, ANDREW JAMES; HOPKINS, ANDREW BRIAN THOMAS; MCDONALD-MAIER, KLAUS DIETER
To: ULTRASOC TECHNOLOGIES LIMITED, A UNITED KINGDOM COMPANY
Reel/Frame 024366/0500 →
Assignment of Assignor's Interest Feb 6, 2013
From: HOPKINS, ANDREW BRIAN THOMAS; BARLOW, STEPHEN JOHN; KRASIC, CONSTANTINE
To: ULTRASOC TECHNOLOGIES, LTD.
Reel/Frame 029763/0115 →
Assignment of Assignor's Interest Jul 9, 2013
From: HOPKINS, ANDREW BRIAN THOMAS
To: ULTRASOC TECHNOLOGIES LTD.
Reel/Frame 030762/0494 →
Assignment of Assignor's Interest Jul 9, 2013
From: HOPKINS, ANDREW BRIAN THOMAS
To: ULTRASOC TECHNOLOGIES LTD.
Reel/Frame 030762/0343 →
Assignment of Assignor's Interest Jul 9, 2013
From: HOPKINS, ANDREW BRIAN THOMAS
To: ULTRASOC TECHNOLOGIES LTD.
Reel/Frame 030762/0564 →
Assignment of Assignor's Interest Jul 9, 2013
From: HOPKINS, ANDREW BRIAN THOMAS
To: ULTRASOC TECHNOLOGIES LTD.
Reel/Frame 030762/0609 →
Assignment of Assignor's Interest Jul 10, 2013
From: HOPKINS, ANDREW BRIAN THOMAS
To: ULTRASOC TECHNOLOGIES LTD.
Reel/Frame 030767/0481 →
Assignment of Assignor's Interest Jul 15, 2013
From: HOPKINS, ANDREW BRIAN THOMAS; BANERJEE, ARNAB; BARLOW, STEPHEN JOHN; MCDONALD-MAIER, KLAUS DIETER
To: ULTRASOC TECHNOLOGIES LTD.
Reel/Frame 030795/0892 →
Assignment of Assignor's Interest Apr 11, 2014
From: HOPKINS, ANDREW BRIAN THOMAS; ROBERTSON, IAIN CRAIG
To: ULTRASOC TECHNOLOGIES LIMITED
Reel/Frame 032659/0746 →
Assignment of Assignor's Interest Apr 11, 2014
From: HOPKINS, ANDREW BRIAN THOMAS; ROBERTSON, IAIN CRAIG
To: ULTRASOC TECHNOLOGIES LIMITED
Reel/Frame 032659/0074 →
Assignment of Assignor's Interest Apr 11, 2014
From: HOPKINS, ANDREW BRIAN THOMAS; ROBERTSON, IAIN CRAIG; THYER, MICHAEL JONATHAN
To: ULTRASOC TECHNOLOGIES LIMITED
Reel/Frame 032658/0254 →
Assignment of Assignor's Interest Oct 9, 2015
From: HOPKINS, ANDREW BRIAN THOMAS; ROBERTSON, IAIN CRAIG; THYER, MICHAEL JONATHAN
To: ULTRASOC TECHNOLOGIES LIMITED
Reel/Frame 036766/0564 →
Assignment of Assignor's Interest Jan 27, 2016
From: HOPKINS, ANDREW BRIAN THOMAS
To: ULTRASOC TECHNOLOGIES LTD.
Reel/Frame 037601/0387 →
Assignment of Assignor's Interest Oct 25, 2016
From: HOPKINS, ANDREW BRIAN THOMAS; BOWER, ANDREW JAMES; THYER, MICHAEL JONATHAN
To: ULTRASOC TECHNOLOGIES LIMITED
Reel/Frame 040114/0211 →
Assignment of Assignor's Interest Oct 25, 2016
From: HOPKINS, ANDREW BRIAN THOMAS; THYER, MICHAEL JONATHAN; ROBERTSON, IAIN CRAIG
To: ULTRASOC TECHNOLOGIES LIMITED
Reel/Frame 040114/0061 →
Assignment of Assignor's Interest Oct 25, 2016
From: HOPKINS, ANDREW BRIAN THOMAS; BOWER, ANDREW JAMES; THYER, MICHAEL JONATHAN
To: ULTRASOC TECHNOLOGIES LIMITED
Reel/Frame 040114/0325 →
Assignment of Assignor's Interest Feb 27, 2020
From: HOPKINS, ANDREW BRIAN; ROBERTSON, IAIN CRAIG
To: ULTRASOC TECHNOLOGIES LIMITED
Reel/Frame 051953/0485 →
Corrective Assignment to Correct the Assignor's Full Name Previously Recorded on Reel 051953 Frame 0485. Assignor(S) Hereby Confirms the Assignor's Full Name Is Andrew Brian Thomas Hopkins. Aug 31, 2020
From: HOPKINS, ANDREW BRIAN THOMAS; ROBERTSON, IAIN CRAIG
To: ULTRASOC TECHNOLOGIES LIMITED
Reel/Frame 053648/0904 →
Merger and Change of Name Apr 9, 2021
From: MENTOR GRAPHICS CORPORATION; SIEMENS INDUSTRY SOFTWARE INC.
To: SIEMENS INDUSTRY SOFTWARE INC.
Reel/Frame 055883/0078 →
Merger and Change of Name Oct 7, 2021
From: MENTOR GRAPHICS CORPORATION; SIEMENS INDUSTRY SOFTWARE INC.
To: SIEMENS INDUSTRY SOFTWARE INC.
Reel/Frame 057731/0158 →