Routing debug messages
An integrated circuit chip device comprising: system circuitry; debugging circuitry configured to debug the system circuitry, the debugging circuitry being segmented into zones; wherein the debugging circuitry comprises an interconnect fabric configured to route debug messages through a zone from a zone entry node of the interconnect fabric to a zone exit node of the interconnect fabric; and wherein the debugging circuitry is configured to, on receiving a debug message at a zone entry node that is shorter than a specified length, modify the debug message to form a modified debug message by increasing the length of the debug message to the specified length.
1. An integrated circuit chip device comprising:
system circuitry;
debugging circuitry configured to debug the system circuitry, the debugging circuitry being segmented into zones;
wherein the debugging circuitry comprises an interconnect fabric configured to route debug messages through a zone from a zone entry node of the interconnect fabric to a zone exit node of the interconnect fabric; and
wherein the debugging circuitry is configured to, on receiving a debug message at a zone entry node that is shorter than a specified length, modify the debug message to form a modified debug message by increasing the length of the debug message to the specified length.
2. An integrated circuit chip device as claimed in claim 1 , wherein the zones are power zones, and one zone is configured to be in a high power mode whilst another zone is configured to be in a low power mode, and wherein the debugging circuitry is configured to receive the debug message at the zone entry node from a zone which transitioned from a high power mode to a low power mode whilst sending the debug message.
3. An integrated circuit chip device as claimed in claim 1 , wherein the debugging circuitry is configured to receive the debug message from a portion of the system circuitry which transitioned from a high power mode to a low power mode whilst sending the debug message.
4. An integrated circuit chip device as claimed in claim 1 , wherein the zone entry node is configured to modify the debug message.
5. An integrated circuit chip device as claimed in claim 1 , wherein the zone exit node is configured to modify the debug message.
6. An integrated circuit chip device as claimed in claim 1 , wherein the debugging circuitry comprises debug units, and wherein the interconnect fabric is configured to route the debug message from a debug unit to a debug controller.
7. An integrated circuit chip device as claimed in claim 6 , further comprising the debug controller.
8. An integrated circuit chip device as claimed in claim 1 , wherein the debugging circuitry comprises a destination unit, and wherein the interconnect fabric is configured to route the debug message to the destination unit, and wherein the destination unit is configured to not change its configuration in response to receiving a modified debug message.
9. An integrated circuit chip device as claimed in claim 1 , wherein the system circuitry and debugging circuitry are integrated on the same integrated circuit chip.
10. An integrated circuit chip device as claimed in claim 1 , wherein the system circuitry and debugging circuitry are comprised across two or more integrated circuit chips of a multi-chip module.
11. A method of routing debug messages through an integrated circuit chip device comprising system circuitry and debugging circuitry, the debugging circuitry being segmented into zones, the debugging circuitry comprising an interconnect fabric, the method comprising:
debugging the system circuitry;
routing debug messages through a zone of the debugging circuitry from a zone entry node of the interconnect fabric to a zone exit node of the interconnect fabric;
receiving a debug message at a zone entry node that is shorter than a specified length; and
modifying the debug message to form a modified debug message by increasing the length of the debug message to the specified length.
12. A method as claimed in claim 11 , comprising outputting the modified debug message from the zone exit node.
13. A method as claimed in claim 11 , wherein the zones are power zones, the method comprising powering one zone in a high power mode whilst powering another zone in a low power mode.
14. A method as claimed in claim 13 , comprising receiving the debug message from a zone which transitioned from a high power mode to a low power mode whilst sending the debug message.
15. A method as claimed in claim 11 , comprising receiving the debug message from a portion of the system circuitry which transitioned from a high power mode to a low power mode whilst sending the debug message.
16. A method as claimed in claim 11 , comprising determining that the debug message is shorter than the specified length by:
counting the number of bytes in the debug message;
comparing the counted number of bytes to the specified length; and
determining that the counted number of bytes is less than the specified length.
17. A method as claimed in claims 11 , comprising, at the zone entry node:
determining that the debug message is shorter than the specified length; and
adding a termination marker to the debug message to identify the end of the debug message.
18. A method as claimed in claim 11 , comprising adding a corruption marker to the debug message to indicate that the debug message is corrupted.
19. A method as claimed in claim 18 , comprising at the zone exit node, discarding debug messages which have been indicated as corrupted by a corruption marker.
20. A method as claimed in claim 11 , comprising routing the debug message to an off-chip debug controller.