Integrated circuit security

1. An integrated circuit having a security supervision system, the integrated circuit comprising:

a plurality of functional circuit blocks mutually interconnected so as to be capable of collectively performing data processing tasks;

one or more communication adaptors, the one or more communication adaptors each having: (i) a hardware interconnection to at least one of the plurality of functional circuit blocks, whereby the communication adaptor is capable of sensing the state and/or activity of the at least one of the plurality of functional circuit blocks; (ii) memory configured to store definitions of state and/or activity of the at least one of the plurality of functional circuit blocks and actions corresponding to each definition; and (iii) processing circuitry configured to compare the state and/or activity of the at least one of the plurality of functional circuit blocks with each definition in parallel with the execution of a command from the said at least one of the plurality of functional circuit blocks, the processing circuitry being configured to, when state and/or activity of the at least one of the plurality of functional circuit blocks corresponding to a stored definition is detected, perform the corresponding action;

the memory being configured to store a definition of state and/or activity characteristic of insecure operation of the at least one of the plurality of functional circuit blocks and a corresponding action that is one of (i) at least partially disabling the at least one of the plurality of functional circuit blocks and (ii) causing a message to be transmitted; and

wherein the integrated circuit further comprises an access controller, the access controller being capable of configuring the memory of a communication adaptor, and being arranged to:

receive a command to configure the memory of a communication adaptor with a configuration comprising a definition of state and/or activity characteristic of insecure operation of the at least one of the plurality of functional circuit blocks and a corresponding action;

attempt to authenticate that command; and

configure the memory of the communication adaptor only if the command is successfully authenticated.

2. The integrated circuit of claim 1 , wherein the processing circuitry of the one or more communication adaptors is implemented in hardware operating in a separate clock domain to the at least one of the plurality of functional circuit blocks to which the communication adaptor is connected.

3. The integrated circuit of claim 1 , wherein the processing circuitry of the communication adaptor is implemented in separate hardware from the plurality of functional circuit blocks.

4. The integrated circuit of claim 3 , wherein the processing circuitry of the communication adaptor is implemented in hardware that is distinct from any hardware on which arbitrary software can run.

5. The integrated circuit of claim 1 , wherein the access controller is arranged to decrypt the command.

6. The integrated circuit of claim 1 , the integrated circuit being configured so that the memory of the communication adaptor is configurable only by the access controller.

7. The integrated circuit of claim 1 , wherein the integrated circuit is arranged to encrypt the message.

8. The integrated circuit of claim 1 , wherein the plurality of functional circuit blocks comprise one or more of a microprocessor, a memory and a communication interface.

9. The integrated circuit of claim 1 , wherein each of the plurality of functional circuit blocks is one or more of a microprocessor, a memory and a communication interface.

10. The integrated circuit of claim 1 , wherein the state and/or activity characteristic of insecure operation of the at least one of the plurality of functional circuit blocks is an attempt to read or write a memory location identified by a predetermined logic.

11. The integrated circuit of claim 1 , wherein the state and/or activity characteristic of insecure operation of the at least one of the plurality of functional circuit blocks is an attempt by a process having a predetermined characteristic to read or write a predetermined memory location.

12. The integrated circuit of claim 1 , wherein the state and/or activity characteristic of insecure operation of the at least one of the plurality of functional circuit blocks is that software stored for execution on the at least one of the plurality of functional circuit blocks matches or fails to match one or more predetermined criteria.

13. The integrated circuit of claim 1 , wherein the state and/or activity characteristic of insecure operation of the at least one of the plurality of functional circuit blocks is that the environment of the integrated circuit matches or fails to match one or more predetermined criteria.

14. The integrated circuit of claim 1 , wherein the integrated circuit stores data associating at least one memory area with at least one process capable of being supported by the at least one of the plurality of functional circuit blocks, and the state and/or activity characteristic of insecure operation of the at least one of the plurality of functional circuit blocks is an attempt by such a process to read or write to that memory area.

15. The integrated circuit of claim 1 , wherein the memory is configured to store a definition of state and/or activity characteristic of secure operation of the at least one of the plurality of functional circuit blocks and a corresponding action that is to log activity of the at least one of the plurality of functional circuit blocks subsequent to that action.

16. An integrated circuit having a security supervision system, the integrated circuit comprising:

a plurality of functional circuit blocks mutually interconnected so as to be capable of collectively performing data processing tasks;

one or more communication adaptors having a hardware interconnection to at least one of the plurality of functional circuit blocks, whereby the one or more communication adaptors is capable of sensing the state and/or activity of the at least one of the plurality of functional circuit blocks; and

a supervisory node coupled for communication with each of the one or more communication adaptors to receive messages from the one or more communication adaptors indicative of the state and/or activity of the plurality of functional circuit blocks, the supervisory node comprising (i) memory configured to store definitions of the state and/or activity of the at least one of the plurality of functional circuit blocks and actions corresponding to each definition; and (ii) processing circuitry configured to compare the state and/or activity indicated by the messages with each definition in parallel with the execution of a command from the said at least one of the plurality of functional circuit blocks, the processing circuitry being configured to, when it detects that state and/or activity indicated by the messages corresponds to a stored definition, perform the corresponding action;

the memory being configured to store a definition of state and/or activity characteristic of insecure operation of the plurality of functional circuit blocks and a corresponding action that is one of (i) at least partially disabling one or more of the plurality of functional circuit blocks and (ii) causing a message to be transmitted;

wherein the integrated circuit further comprises an access controller, the access controller being capable of configuring the memory of the supervisory node, and being arranged to:

receive a command to configure the memory of the supervisory node with a configuration comprising a definition of state and/or activity characteristic of insecure operation of the at least one of the plurality of functional circuit blocks and a corresponding action;

attempt to authenticate that command; and

configure the memory of the supervisory node only if the command is successfully authenticated.