Error detection within an integrated circuit chip

1. A method of performing error detection within an integrated circuit chip, comprising:

analyzing transactions communicated over interconnect circuitry of the integrated circuit chip to detect whether a transaction contains a data error, wherein the analyzing comprises performing, on one or more messages of each transaction, a parity check to detect whether a message of the one or more messages contains a data error, or a cyclic redundancy check to detect whether the message contains a data error;

scanning a memory of the integrated circuit chip coupled to the interconnect circuitry to detect whether there is a data error stored in the memory, wherein the scanning is performed at times when the interconnect circuitry is free; and

in response to detecting a data error in a transaction communicated over the interconnect circuitry and/or a data error stored in the memory, performing a dedicated action indicative of a data error.

2. The method as claimed in claim 1 , wherein the step of scanning the memory of the integrated circuit chip is performed by detection circuitry coupled to the interconnect circuitry.

3. The method as claimed in claim 1 , wherein the step of scanning the memory of the integrated circuit chip comprises scanning one or more blocks of the memory to detect whether the one or more blocks contain a data error by:

scanning that block of the memory at a first time;

generating a first characterization of the data read from the block at the first time and storing that first characterization;

scanning that block of memory at a second time subsequent to the first time;

generating a second characterization of the data read from the block at the second time and comparing the second characterization to the first characterization; and

detecting that the data in the block contains an error if the first and second characterizations do not match.

4. The method as claimed in claim 3 , wherein the block of memory is scanned at the second time only if no data has been written to that block between the first time and the second time.

5. The method as claimed in claim 3 , wherein the first characterization is a first hash value generated from the data read from the block at the first time, and the second characterization is a second hash value generated from the data read from the block at the second time.

6. The method as claimed in claim 3 , wherein the method comprises scanning a block of the memory to detect whether that block contains a data error in response to detecting that the block is scheduled to be used in a communication over the interconnect circuitry.

7. The method as claimed in claim 6 , wherein the method comprises detecting that the block is scheduled to be used in a communication over the interconnect circuitry in response to identifying a message of a transaction over the interconnect circuitry specifying an address within that block.

8. The method as claimed in claim 3 , wherein the one or more scanned blocks of memory comprise blocks of read-only memory.

9. The method as claimed in claim 1 , wherein the step of scanning the memory of the integrated circuit chip comprises scanning one or more blocks of the memory to detect whether the one or more blocks contain a data error by:

scanning that block of memory at a first time;

generating a first characterization of the data read from the block at the first time and storing that first characterization;

scanning that block of memory at a second time subsequent to the first time;

generating a second characterization of the data read from the block at the second time and comparing the second characterization to the first characterization; and

detecting that the data in the block contains an error if the first and second characterizations do match.

10. The method as claimed in claim 9 , wherein the first characterization is a first hash value generated from the data read from the block at the first time, and the second characterization is a second hash value generated from the data read from the block at the second time.

11. The method as claimed in claim 1 , wherein the dedicated action performed in response to detecting data error in the memory comprises one or more of:

correcting the error in the data and writing the corrected data back to the memory;

generating an alert signal; and

blocking access to the data error in the memory.

12. The method as claimed in claim 1 , wherein the dedicated action performed in response to detecting a data error in a message of a transaction communicated over the interconnect circuitry comprises one or more of:

correcting the error and communicating a message containing corrected data;

communicating an indication of the error to an entity from which the message was communicated; and

generating an alert signal.

13. The method as claimed in claim 1 , wherein the method further comprises recording information associated with detected data errors in transactions communicated over the interconnect circuitry and/or detected data errors stored in the memory over time to generate an error profile.

14. The method as claimed in claim 13 , wherein the method comprises analyzing transactions communicated over the interconnect circuitry selected in dependence on the error profile.

15. The method as claimed in claim 13 , wherein the step of scanning the memory of the integrated circuit chip comprises scanning one or more blocks of the memory to detect whether the one or more blocks contain a data error,

wherein the one or more blocks of the memory are selected in dependence on the error profile, and

wherein the method comprises scanning the memory at selected times in dependence on the error profile.

16. The method as claimed in claim 1 , further comprising recording information indicative of activity levels of the interconnect circuitry and/or memory over time to generate an activity profile.

17. The method as claimed in claim 16 , wherein the method comprises analyzing transactions communicated over the interconnect circuitry within a time interval indicated by the activity profile to have a level of activity exceeding a specified threshold.

18. The method as claimed in claim 16 , wherein the step of scanning the memory of the integrated circuit chip comprises scanning one or more blocks of the memory to detect whether the one or more blocks contain a data error, and the method comprises scanning one or more blocks of memory selected in dependence on the activity profile and/or scanning the memory at selected times in dependence on the activity profile.

19. The method as claimed in claim 1 , wherein, when the cyclic redundancy check is performed, the message communicated over the interconnect circuitry includes a check value, and wherein the check value depends upon a remaining content of the message.

20. The method as claimed in claim 19 , further comprising:

checking the transaction using a transaction check unit;

analyzing, by the transaction check unit, the message by re-calculating the check value based on the content of the message; and

comparing, by the transaction check unit, the re-calculated check value to the check value within the message.

21. The method as claimed in claim 19 , further comprising:

detecting, by the transaction check unit, that the message does not contain a data error when the check values match; and

detecting, by the transaction check unit, that the message does contain a data error when the check values do not match.

22. An integrated circuit chip, comprising:

interconnect circuitry configured to transport messages;

a memory coupled to the interconnect circuitry; and

detection circuitry configured to:

analyze transactions communicated over interconnect circuitry of the integrated circuit chip to detect whether there is a data error stored in the memory, the analysis of the transactions comprising performing, on one or more messages of each transaction, of a parity check to detect whether that message contains a data error, or a cyclic redundancy check to detect whether that message contains a data error;

scan the memory at times when the interconnect circuitry is free to detect whether data stored in the memory contains an error; and

in response to detecting a data error in a transaction communicated over the interconnect circuitry and/or an error in the data stored in the memory, perform a dedicated action indicative of a data error.