Debug adapter

1. An integrated circuit chip comprising:

system circuitry comprising a peripheral circuit;

debugging circuitry comprising:

a debug unit connected to the peripheral circuit; and

a debug adapter configured to interface between the debug unit and a debug controller, and configured to:

receive a sequence of debug commands from the debug controller, each debug command instructing the debug unit to perform an action other than responding to a poll; and

in respect of each debug command:

send the debug command to the debug unit; and

poll the debug unit to query whether the debug unit has performed the action instructed in that debug command.

2. An integrated circuit chip as claimed in claim 1 , the debug adapter further being configured to, in respect of each debug command:

receive a poll response from the debug unit; and

if that poll response indicates that the debug unit has performed the action, send the next debug command in the sequence of debug commands to the debug unit.

3. An integrated circuit chip as claimed in claim 1 , the debug adapter further being configured to, in respect of each debug command:

receive a poll response from the debug unit; and

if that poll response indicates that the debug unit has not performed the action:

repeatedly poll the debug unit to query whether the debug unit has performed the action instructed in that debug command; and

on receiving a poll response indicating that the debug unit has performed the action, send the next debug command in the sequence of debug commands to the debug unit.

4. An integrated circuit chip as claimed in claim 1 , the debug adapter comprising a buffer, the debug adapter being configured to:

store the sequence of debug commands in the buffer; and

in respect of each debug command, on receiving a poll response from the debug unit indicating that the debug unit has performed the action, extract the next debug command in the sequence of commands from the buffer for transmittal to the debug unit.

5. An integrated circuit chip as claimed in claim 1 , the debug adapter being configured to receive the sequence of debug commands in a single communication from the debug controller.

6. An integrated circuit chip as claimed in claim 1 , the debug adapter comprising a memory, the debug adapter being configured to:

prior to debugging the system circuitry, receive sequences of debug commands from the debug controller to be pre-loaded to the memory;

pre-load the sequences of debug commands to the memory;

subsequently receive an instruction from the debug controller to execute a pre-loaded debug command sequence; and

extract that pre-loaded debug command sequence from the memory and send the debug commands of that pre-loaded debug command sequence to the debug unit.

7. An integrated circuit chip as claimed in claim 6 , the debug adapter being configured to:

whilst debugging the system circuitry, receive a memory update from the debug controller comprising a further debug command sequence to be loaded to the memory;

load the further debug command sequence to the memory; and

on receiving an instruction from the debug controller to execute the further debug command sequence, extract the further debug command sequence from the memory and send the debug commands of that further debug command sequence to the debug unit.

8. An integrated circuit chip as claimed in claim 1 , the debug adapter comprising a register, the debug adapter being configured to read a data value from the debug unit and store the data value in the register.

9. An integrated circuit chip as claimed in claim 8 , the debug adapter being further configured to perform a logical or arithmetic operation on the data value.

10. An integrated circuit chip as claimed in claim 8 , the debug adapter being further configured to select a further debug command to send to the debug unit in dependence on the data value.

11. An integrated circuit chip as claimed in claim 1 , the debug adapter being further configured to selectively poll the debug unit to query whether the debug unit has performed the action instructed in the debug command in dependence on the debug command type.

12. An integrated circuit chip as claimed in claim 11 , wherein the debug adapter is configured to select not to poll the debug unit following sending a debug command which the debug unit is configured to respond to by sending data to the debug controller.

13. A method of debugging an integrated circuit chip, the integrated circuit chip comprising system circuitry and debugging circuitry, the system circuitry comprising a peripheral circuit, and the debugging circuitry comprising a debug unit and a debug adapter, the debug unit connected to the peripheral circuit, the debug adapter configured to interface between the debug unit and a debug controller, the method comprising, at the debug adapter:

receiving a sequence of debug commands from the debug controller, each debug command instructing the debug unit to perform an action other than responding to a poll; and

in respect of each debug command:

sending the debug command to the debug unit; and

polling the debug unit to query whether the debug unit has performed the action instructed in that debug command.

14. A method as claimed in claim 13 , further comprising, in respect of each debug command:

receiving a poll response from the debug unit; and

if that poll response indicates that the debug unit has performed the action, sending the next debug command in the sequence of debug commands to the debug unit.

15. A method as claimed in claim 13 , further comprising, in respect of each debug command:

receiving a poll response from the debug unit; and

if that poll response indicates that the debug unit has not performed the action:

repeatedly polling the debug unit to query whether the debug unit has performed the action instructed in that debug command; and

on receiving a poll response indicating that the debug unit has performed the action, sending the next debug command in the sequence of debug commands to the debug unit.

16. A method as claimed in claim 13 , further comprising:

storing the sequence of debug commands in a buffer; and

in respect of each debug command, on receiving a poll response from the debug unit indicating that the debug unit has performed the action, extracting the next debug command in the sequence of commands from the buffer for transmittal to the debug unit.

17. A method as claimed in claim 13 , further comprising receiving the sequence of debug commands in a single communication from the debug controller.

18. A method as claimed in claim 13 , further comprising:

prior to debugging the system circuitry, receiving sequences of debug commands from the debug controller to be pre-loaded to a memory;

pre-loading the sequences of debug commands to the memory;

subsequently receiving an instruction from the debug controller to execute a pre-loaded debug command sequence; and

extracting that pre-loaded debug command sequence from the memory and sending the debug commands of that pre-loaded debug command sequence to the debug unit.

19. A method as claimed in claim 18 , comprising:

whilst debugging the system circuitry, receiving a memory update from the debug controller comprising a further debug command sequence to be loaded to the memory;

loading the further debug command sequence to the memory; and

on receiving an instruction from the debug controller to execute the further debug command sequence, extracting the further debug command sequence from the memory and sending the debug commands of that further debug command sequence to the debug unit.

20. A method as claimed in claim 13 , comprising, at the debug adapter, reading a data value from the debug unit and storing the data value in the register.