Functional testing of an integrated circuit chip

1. An integrated circuit chip comprising:

system circuitry configured to perform a function, the system circuitry comprising a plurality of sub-circuits configured to perform the function by performing concurrent actions;

debugging circuitry configured to detect one or more errors in the system circuitry's performance of the function, the debugging circuitry comprising variability circuitry;

wherein the debugging circuitry is configured to functionally test the system circuitry by:

at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function, wherein the relative timing of the concurrent actions is altered by applying an error to one or more of the concurrent actions; and

where one or more errors are found, recording the one or more errors.

2. An integrated circuit chip as claimed in claim 1 , wherein the variability circuitry is configured to apply the error where the error is detectable by the system circuitry.

3. An integrated circuit chip as claimed in claim 2 , wherein the system circuitry is configured to respond to detecting the error by implementing an accommodating procedure.

4. An integrated circuit chip as claimed in claim 3 , wherein the system circuitry is configured to implement the accommodating procedure by retrying the function.

5. An integrated circuit chip as claimed in claim 3 , wherein the system circuitry is configured to implement the accommodating procedure by implementing a recovery operation.

6. An integrated circuit chip as claimed in claim 1 , wherein the variability circuitry is further configured to alter the relative timing of the concurrent actions by applying jitter to the timing of the concurrent actions.

7. An integrated circuit chip as claimed in claim 1 , wherein the variability circuitry is further configured to alter the relative timing of the concurrent actions by applying a delay to occurrences of a particular action of the concurrent actions.

8. An integrated circuit chip as claimed in claim 1 , wherein the system circuitry comprises a clock, and the variability circuitry is further configured to alter the relative timing of the concurrent actions by modifying the frequency or phase of the clock output.

9. An integrated circuit chip as claimed in claim 8 , wherein the system circuitry comprises clock gating circuitry at an output of the clock, and the variability circuitry is further configured to modify the frequency of the clock output by controlling the clock gating circuitry to delete clock pulses output from the clock.

10. An integrated circuit chip as claimed in claim 1 , wherein the system circuitry comprises interconnect circuitry, and wherein the sub-circuits are configured to perform the concurrent actions by communicating signals on the interconnect circuitry, and wherein the variability circuitry is further configured to alter the relative timing of the concurrent actions by intercepting or delaying the signals on the interconnect circuitry.

11. An integrated circuit chip as claimed in claim 1 , wherein the system circuitry comprises a cache, and wherein the sub-circuits are configured to perform the concurrent actions using the cache, and wherein the variability circuitry is further configured to alter the relative timing of the concurrent actions by invalidating cache lines of the cache.

12. An integrated circuit chip as claimed in claim 1 , wherein the system circuitry comprises a processor, and wherein the variability circuitry is further configured to alter the relative timing of the concurrent actions by stopping the processor for a time duration.

13. An integrated circuit as claimed in claim 1 , wherein the debugging circuitry is configured to functionally test the system by:

causing the system circuitry to repeatedly perform the function; and

at the variability circuitry, on each repeat performance of the function, altering the relative timing of the concurrent actions such that the likelihood of one or more errors in the system circuitry's performance of the function is higher than that likelihood for the last repeat performance of the function; and

where one or more errors are found, recording the one or more errors.

14. An integrated circuit as claimed in claim 13 , wherein the debugging circuitry is configured to determine minimum system resources required by the system circuitry in order to perform the function in dependence on the functional test.

15. An integrated circuit as claimed in claim 1 , wherein the variability circuitry is further configured to alter the relative timing of the concurrent actions in response to debug events occurring on the integrated circuit chip.

16. An integrated circuit chip as claimed in claim 1 , wherein the variability circuitry comprises a counter for altering the relative timing of the concurrent actions.

17. An integrated circuit chip as claimed in claim 1 , wherein the variability circuitry comprises a linear-feedback shift register for altering the relative timing of the concurrent actions.

18. An integrated circuit chip as claimed in claim 1 , wherein the variability circuitry comprises a pseudo-random number generator for altering the relative timing of the concurrent actions.

19. A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry, the method comprising:

at the system circuitry, performing a function by the sub-circuits performing concurrent actions;

at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function, wherein the relative timing of the concurrent actions is altered by applying an error to one or more of the concurrent actions; and

at the debugging circuitry, recording one or more errors that may be found in the system circuitry's performance of the function.

20. A method as claimed in claim 19 , comprising:

at the variability circuitry, applying the error where the error is detectable by the system circuitry; and

at the system circuitry, responding to detecting the error by implementing an accommodating procedure.

21. An integrated circuit chip comprising:

system circuitry configured to perform a function, the system circuitry comprising a plurality of sub-circuits configured to perform the function by performing concurrent actions;

debugging circuitry configured to detect one or more errors in the system circuitry's performance of the function, the debugging circuitry comprising variability circuitry;

wherein the debugging circuitry is configured to functionally test the system circuitry by: at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function, wherein the relative timing of the concurrent actions is altered by applying a delay to occurrences of a particular action of the concurrent actions by intercepting or delaying a communication through system circuitry; and

where one or more errors are found, recording the one or more errors.

22. An integrated circuit chip as claimed in claim 21 , wherein the variability circuitry is further configured to alter the relative timing of the concurrent actions by applying jitter to the timing of the concurrent actions.

23. An integrated circuit chip as claimed in claim 21 , wherein the system circuitry comprises a clock, and the variability circuitry is further configured to alter the relative timing of the concurrent actions by modifying the frequency or phase of the clock output.

24. . An integrated circuit chip as claimed in claim 23 , wherein the system circuitry comprises clock gating circuitry at an output of the clock, and the variability circuitry is further configured to modify the frequency of the clock output by controlling the clock gating circuitry to delete clock pulses output from the clock.

25. An integrated circuit chip as claimed in claim 21 , wherein the system circuitry comprises interconnect circuitry, and wherein the sub-circuits are configured to perform the concurrent actions by communicating signals on the interconnect circuitry, and wherein the variability circuitry is further configured to alter the relative timing of the concurrent actions by intercepting or delaying the signals on the interconnect circuitry.

26. An integrated circuit chip as claimed in claim 21 , wherein the variability circuitry is further configured to alter the relative timing of the concurrent actions by applying an error to one or more of the concurrent actions.

27. An integrated circuit chip as claimed in claim 21 , wherein the system circuitry comprises a cache, and wherein the sub-circuits are configured to perform the concurrent actions using the cache, and wherein the variability circuitry is further configured to alter the relative timing of the concurrent actions by invalidating cache lines of the cache.

28. An integrated circuit chip as claimed in claim 21 , wherein the system circuitry comprises a processor, and wherein the variability circuitry is further configured to alter the relative timing of the concurrent actions by stopping the processor for a time duration.

29. An integrated circuit as claimed in claim 21 , wherein the debugging circuitry is configured to functionally test the system by:

causing the system circuitry to repeatedly perform the function; and

at the variability circuitry, on each repeat performance of the function, altering the relative timing of the concurrent actions such that the likelihood of one or more errors in the system circuitry's performance of the function is higher than that likelihood for the last repeat performance of the function; and

where one or more errors is found, recording the one or more errors.

30. An integrated circuit as claimed in claim 29 , wherein the debugging circuitry is configured to determine minimum system resources required by the system circuitry in order to perform the function in dependence on the functional test.

31. An integrated circuit as claimed in claim 21 , wherein the variability circuitry is further configured to alter the relative timing of the concurrent actions in response to debug events occurring on the integrated circuit chip.

32. An integrated circuit chip as claimed in claim 21 , wherein the variability circuitry comprises a counter for altering the relative timing of the concurrent actions.

33. An integrated circuit chip as claimed in claim 21 , wherein the variability circuitry comprises a linear-feedback shift register for altering the relative timing of the concurrent actions.

34. An integrated circuit chip as claimed in claim 21 , wherein the variability circuitry comprises a pseudo-random number generator for altering the relative timing of the concurrent actions.

35. A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry, the method comprising:

at the system circuitry, performing a function by the sub-circuits performing concurrent actions;

at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function, wherein the relative timing of the concurrent actions is altered by applying a delay to occurrences of a particular action of the concurrent actions by intercepting or delaying a communication through system circuitry; and

at the debugging circuitry, recording one or more errors that may be found in the system circuitry's performance of the function.

36. A method as claimed in claim 35 , comprising further altering the relative timing of the concurrent actions by applying jitter to the timing of the concurrent actions.

37. A method as claimed in claim 35 , comprising applying the delay to every occurrence of the particular action of the concurrent actions.

38. A method as claimed in claim 35 , comprising applying the delay to a proportion of the occurrences of the particular action of the concurrent actions.