Debug architecture

1. A method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, a communication adapter and a shared hub, the shared hub being accessible by the access controller, the plurality of peripheral circuits, and the communication adapter, the method comprising:

prior to authenticating the debug controller, preventing unauthenticated communications from the debug controller being routed to the shared hub with the exception of authentication communications;

at the access controller, receiving an authentication request routed through the shared hub, and, authenticating the debug controller;

at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and

after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights;

wherein all authentication communications between the debug controller and the access controller are routed through the shared hub and the communication adapter.

2. A method as claimed in claim 1 , further comprising implementing the set of access rights by asserting and/or deasserting locks on links between the shared hub and the peripheral circuits.

3. A method as claimed in claim 2 , wherein an asserted lock on a link between the shared hub and a peripheral circuit prevents the passage of data on that link from the debug controller to the peripheral circuit.

4. A method as claimed in claim 2 , wherein an asserted lock on a link between the shared hub and a peripheral circuit prevents the debug controller from controlling the peripheral circuit to perform an action.

5. A method as claimed in claim 2 , wherein an asserted lock on a link between the shared hub and a system memory prevents the shared hub from accessing the system memory.

6. A method as claimed in claim 1 , further comprising at the access controller:

storing predetermined sets of access rights; and

recording the set of access rights currently assigned to the debug controller.

7. A method as claimed in claim 1 , wherein the debug architecture further comprises a stream frame buffer configured to receive communications from the debug controller, the method further comprising at the stream frame buffer:

routing authentication communications received from the debug controller to the access controller;

prior to authenticating the debug controller, discarding unauthenticated communications received from the debug controller with the exception of authentication communications; and

after authenticating the debug controller, routing authenticated communications received from the debug controller to the shared hub.

8. A method as claimed in claim 1 , further comprising, following authentication, encrypting communications between the debug architecture and the debug controller.

9. A method as claimed in claim 1 , further comprising, at the access controller:

authenticating a further debug controller;

assigning to the further debug controller a further set of access rights granting the further debug controller partial access to the debug architecture; and

removing the assigned set of access rights to the debug controller in response to authenticating the further debug controller.

10. A method as claimed in claim 1 , further comprising, at the access controller:

authenticating a further debug controller;

assigning to the further debug controller a further set of access rights granting the further debug controller partial access to the debug architecture; and

removing the assigned set of access rights to the debug controller if the further set of access rights grant greater access to the debug architecture than the set of access rights.

11. A method as claimed in claim 1 , further comprising, at the access controller:

receiving an authentication request from a further debug controller; and

assigning no access rights to the further debug controller whilst the debug controller is communicating with the debug architecture.

12. A method as claimed in claim 1 , further comprising, at the access controller:

authenticating a further debug controller;

determining a further set of access rights to assign to the further debug controller granting the further debug controller partial access to the debug architecture; and

if the set of access rights grant greater access to the debug architecture than the further set of access rights, assigning no access rights to the further debug controller whilst the debug controller is communicating with the debug architecture.

13. A method as claimed in claim 1 , further comprising, at the access controller:

authenticating a further debug controller; and

assigning to the further debug controller the set of access rights assigned to the debug controller.

14. A method as claimed in claim 1 , further comprising, at the access controller:

authenticating a further debug controller; and

assigning to the further debug controller a further set of access rights granting the further debug controller partial access to the debug architecture.

15. A method as claimed in claim 1 , wherein the debug architecture is hierarchical, the access controller and the shared hub being in a first level of the hierarchy, wherein the debug architecture further comprises a further access controller at a second level of the hierarchy, the further access controller being directly accessible by a further shared hub at the second level of the hierarchy, the method further comprising:

at the further access controller, authenticating the debug controller;

at the further access controller, following authentication, assigning to the debug controller a second set of access rights, the second set of access rights granting the debug controller partial access to the debug architecture; and

after assigning the second set of access rights, allowing the debug controller access to the debug architecture as allowed by the second set of access rights.

16. An integrated circuit chip comprising:

debug architecture comprising an access controller, a plurality of peripheral circuits, a communication adapter, and a shared hub, the shared hub being accessible by the access controller, the plurality of peripheral circuits, and the communication adapter;

the access controller configured to receive an authentication request routed through the shared hub and authenticate a debug controller and, following authentication, assign to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and

the debug architecture configured to after the set of access rights are assigned, allow the debug controller access to the debug architecture as allowed by the set of access rights;

wherein the integrated circuit chip is configured such that all authentication communications between the debug controller and the access controller are routed through the shared hub and the communication adapter and, prior to the debug controller being authenticated by the access controller, prevent unauthenticated communications from the debug controller being routed to the shared hub with the exception of authentication communications.

17. An integrated circuit chip as claimed in claim 16 , further comprising locks on links between the shared hub and the peripheral circuits which are assertable and deassertable so as to implement the set of access rights.

18. An integrated circuit chip as claimed in claim 16 , wherein the access controller further comprises a store configured to store predetermined sets of access rights, and record the set of access rights currently assigned to the debug controller.

19. An integrated circuit chip as claimed in claim 16 , wherein the debug architecture further comprises a stream frame buffer configured to:

route authentication communications received from the debug controller to the access controller;

prior to authenticating the debug controller, discard unauthenticated communications received from the debug controller with the exception of authentication communications; and

after authenticating the debug controller, route authenticated communications received from the debug controller to the shared hub.

20. An integrated circuit chip as claimed in claim 16 , wherein the debug architecture is hierarchical, the access controller and the shared hub being in a first level of the hierarchy, wherein the debug architecture further comprises a further access controller at a second level of the hierarchy, the further access controller being directly accessible by a further shared hub at the second level of the hierarchy;

the further access controller being configured to authenticate the debug controller, and following authentication, to assign to the debug controller a second set of access rights, the second set of access rights granting the debug controller partial access to the debug architecture; and

the debug architecture being configured to after assigning the second set of access rights, allowing the debug controller access to the debug architecture as allowed by the second set of access rights.