IP Library Granted Patent US 8,941,516
Granted Patent B2
US 8,941,516 · App. 13/691,180 · Granted Jan 27, 2015

Signal processing apparatus and signal processing method thereof

Inventors: Jin Mok Kim (Daejeon, KR); Hyukchan Kwon (Daejeon, KR); Yong Ho Lee (Daejeon, KR); Ki Woong Kim (Daejeon, KR)
Assignee: Korea Research Institute of Standards and Science
H03M9/00G06F13/4295
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,941,516
App. No.
13/691,180
Granted
Jan 27, 2015
Kind
B2
Abstract

Provided are a signal processing apparatus and a signal processing method. The signal processing method include receiving a serial signal including an information frame including channel information and data information of a corresponding channel, extracting a clock signal from the serial signal, generating a load signal when a clock count reaches a maximum clock count by calculating the clock signal; converting the serial signal to a parallel signal according to the load signal, and changing the maximum clock count by comparing parallel-converted parallel channel information with a load count indicating the number of local signals.

Claims (46)

1. A signal processing method comprising:

receiving a serial signal including an information frame including channel information and data information of a corresponding channel;

extracting a clock signal from the serial signal;

generating a load signal when a clock count reaches a maximum clock count by calculating the clock signal;

converting the serial signal to a parallel signal according to the load signal; and

changing the maximum clock count by comparing parallel-converted parallel channel information with a load count indicating the number of local signals.

2. The signal processing method as set forth in claim 1 , wherein changing the maximum clock count comprises:

increasing a load count when the load signal is generated;

changing the load count to the parallel channel information when the maximum clock count is different from a set reference value;

changing the maximum clock count when the parallel channel information is different from the load count and setting the maximum clock count to the set reference value when the parallel channel information is identical to the load count; and

resetting the load count when the load count is the set maximum load count.

3. The signal processing method as set forth in claim 1 , wherein generating a load signal when a clock count reaches a maximum clock count by calculating the clock signal comprises:

increasing a clock;

comparing the clock count with the maximum clock count;

generating a load signal when the clock count is the maximum clock count; and

resetting the clock count.

4. The signal processing method as set forth in claim 1 , further comprising:

transmitting the parallel signal to a computer.

5. The signal processing method as set forth in claim 1 , wherein the parallel signal is transmitted through an optical signal.

6. The signal processing method as set forth in claim 1 , wherein the serial signal is transmitted successively and repeatedly, and the parallel signal is converted in real time.

7. A signal processing method comprising:

receiving a serial signal including an information frame including channel information and data information of a corresponding channel; and

extracting a load signal converting the serial signal to a parallel signal from the serial signal and correcting a generation location of the load signal by comparing a load count indicating the number of load signal with parallel-converted parallel channel information.

8. The signal processing method as set forth in claim 7 , wherein a serial signal is converted to a parallel signal by a serial-to-parallel converter, a value of a specific location of a parallel output of the serial-to-parallel converter is set to parallel channel information, the load count is set by calculating the count of the load signal, and a generation location of the load signal is changed by comparing the parallel channel information with the load signal.

9. A signal processing apparatus comprising:

a clock generator configured to receive a serial signal including an information frame including channel information and data information of a corresponding channel to extract a clock signal from the serial signal;

a clock counter configured to receive a clock signal of the clock generator to output a load signal when a clock count reaches a maximum clock count;

a serial-to-parallel converter configured to receive the clock signal, the load signal, and the serial signal to convert the serial signal to a parallel signal according to the load signal; and

a load signal corrector configured to receive the clock signal, the load signal, and parallel channel information of a predetermined location of the parallel signal and to change the maximum clock count.

10. The signal processing apparatus as set forth in claim 9 , wherein the load signal corrector comprises:

a load counter configured to receive and output the parallel channel information and receive directly or indirectly the load signal and output a load count of a generation count of the load signal;

a comparator configured to receive and compare the parallel channel information and the load count and output a compared result; and

a process register unit configured to receive the clock signal of the clock generator to output first to third clock signals.

11. The signal processing apparatus as set forth in claim 10 , wherein the load counter receives and outputs parallel channel information when an output of the comparator is high and the second clock signal is generated.

12. The signal processing apparatus as set forth in claim 9 , wherein the serial signal is an optical signal.

13. The signal processing apparatus as set forth in claim 9 , further comprising:

an optical waveguide configured to transmit the serial signal; and

an optical transmitter configured to provide a serial signal to the optical waveguide.

14. A signal processing apparatus comprising:

a clock generator configured to receive a serial signal including an information frame including channel information and data information of a corresponding channel to extract a clock signal from the serial signal;

a clock counter configured to output a load signal by using the clock signal of the clock generator;

a serial-to-parallel converter configured to receive the load signal and the serial signal to convert the serial signal to a parallel signal according to the load signal; and

a load signal corrector configured to correct a generation location of the load signal by using the load signal and the parallel signal.

15. The signal processing apparatus as set forth in claim 14 , further comprising:

an optical waveguide configured to transmit the serial signal; and

an optical transmitter configured to provide a serial signal to the optical waveguide.

Assignments (5)
CONFIRMATORY TERMINATION OF PATENT LICENSE Recorded Feb 13, 2023
From: BIOMAGNETIK PARK HOLDING GMBH
To: KOREA RESEARCH INSTITUTE OF STANDARDS & SCIENCE
Reel/Frame 062718/0060 →
CHANGE OF NAME Recorded Feb 7, 2023
From: BIOMAGNETIK PARK GMBH
To: BIOMAGNETIK PARK HOLDING GMBH
Reel/Frame 062613/0098 →
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 7456263 PREVIOUSLY RECORDED AT REEL: 038044 FRAME: 0151. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT . Recorded Apr 10, 2017
From: KOREA RESEARCH INSTITUTE OF STANDARDS & SCIENCE
To: BIOMAGNETIK PARK GMBH
Reel/Frame 042201/0033 →
CONFIRMATORY LICENSE Recorded Mar 9, 2016
From: KOREA RESEARCH INSTITUTE OF STANDARDS & SCIENCE
To: BIOMAGNETIK PARK GMBH
Reel/Frame 038044/0151 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 3, 2012
From: KIM, JIN MOK; KWON, HYUKCHAN; LEE, YONG HO; KIM, KI WOONG
To: KOREA RESEARCH INSTITUTE OF STANDARDS AND SCIENCE
Reel/Frame 029394/0473 →
Priority Claims (1)
KR 10-2010-0052238 · Jun 3, 2010 · national
Continuity (2)
Continuation PCTKR2010004904 · Jul 27, 2010
Related Publication 20130093608A1 · Apr 18, 2013