IP Library Granted Patent US 8,617,959
Granted Patent B2
US 8,617,959 · App. 13/691,352 · Granted Dec 31, 2013

Resistive memory and methods of processing resistive memory

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,617,959
App. No.
13/691,352
Granted
Dec 31, 2013
Kind
B2
Abstract

Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include conformally forming a cell material in an opening in an interlayer dielectric such that a seam is formed in the cell material, forming a conductive pathway by modifying the seam, and forming an electrode on the cell material and the seam.

Claims (38)

1. A method of processing a memory cell, comprising:

forming a seam in a cell material;

wherein the seam is formed in the cell material by conformally forming the cell material; and

forming a conductive pathway in the seam.

2. The method of claim 1 , wherein the method includes heating the conductive pathway after forming the conductive pathway in the seam.

3. The method of claim 1 , wherein the method includes removing a portion of the cell material after forming the seam in the cell material.

4. The method of claim 3 , wherein the method includes forming an electrode on the cell material and the seam after removing the portion of the cell material.

5. A method of processing a memory cell, comprising:

conformally forming a cell material such that a seam is formed in the cell material;

wherein the seam is an opening in the cell material; and

modifying the seam, wherein modifying the seam includes forming a filament in the seam.

6. The method of claim 5 , wherein the method includes forming the filament in the seam such that the filament completely fills the seam.

7. A method of processing a memory cell, comprising:

conformally forming a cell material such that a seam is formed in the cell material;

forming a conductive pathway in the seam; and

removing a portion of the conductive pathway.

8. The method of claim 7 , wherein the method includes diffusing atoms from the conductive pathway into the cell material after forming the conductive pathway in the seam.

9. The method of claim 7 , wherein the conductive pathway is a different material than the cell material.

10. The method of claim 7 , wherein forming the conductive pathway in the seam increases a concentration of atoms in the conductive pathway.

11. The method of claim 7 , wherein the method includes forming the conductive pathway in the seam such that an end of the conductive pathway is adjacent to a bottom of the seam.

12. The method of claim 7 , wherein the removed portion of the conductive pathway includes a portion of the conductive pathway that is not in the seam.

13. A memory cell, comprising:

a conformally formed cell material having a seam formed therein; and

a conductive pathway in the seam, wherein the conductive pathway has a diameter of 5.0 nanometers or less.

14. The memory cell of claim 13 , wherein the conductive pathway includes a filament.

15. The memory cell of claim 14 , wherein a thickness of the filament is less than a thickness of the cell material.

16. The memory cell of claim 13 , wherein the cell material is a resistive memory cell material.

17. A memory cell, comprising:

a dielectric material having an opening;

a cell material in the opening;

a seam in the cell material; and

an electrode adjacent the opening, wherein the electrode is not in contact with the seam.

18. The memory cell of claim 17 , wherein the cell material is conformally formed in the opening.

19. The memory cell of claim 17 , wherein the memory cell includes a conductive pathway in the seam.

20. The memory cell of claim 17 , wherein the memory cell includes only cell material between a bottom of the seam and the electrode.

21. The memory cell of claim 17 , wherein a distance between a bottom of the seam and the electrode is 15 Angstroms or less.

22. The memory cell of claim 17 , wherein the cell material conforms to the dielectric material.

23. The memory cell of claim 17 , wherein the opening has a diameter of 30 nanometers or less.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 1, 2016
From: MICRON TECHNOLOGY, INC
To: OVONYX MEMORY TECHNOLOGY, LLC
Reel/Frame 039974/0496 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 3, 2012
From: SANDHU, GURTEJ S.; SMYTHE, JOHN A., III
To: MICRON TECHNOLOGY, INC.
Reel/Frame 029390/0114 →