Method for forming gate structure, method for forming semiconductor device, and semiconductor device
A method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on the substrate; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming a first work function adjustment layer on the oxygen scavenging element layer; etching the first work function adjustment layer above the nMOSFET area; forming a second work function adjustment layer on the surface of the substrate; metal layer depositing and annealing to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.
1. A method for forming a gate structure, comprising:
providing a substrate, wherein the substrate comprises a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer;
forming a gate dielectric capping layer on a surface of the substrate;
forming an etching stop layer on the gate dielectric capping layer;
forming an oxygen scavenging element layer on the etching stop layer;
forming a first work function adjustment layer on the oxygen scavenging element layer;
etching the first work function adjustment layer above the nMOSFET area until the etching stop layer is exposed;
forming a second work function adjustment layer on the surface of the substrate;
performing metal layer deposition and annealing process to fill the gate trenches with a metal layer; and
removing the metal layer outside the gate trenches.
2. The method according to claim 1 , wherein the gate dielectric capping layer has a thickness of 5 angstroms to 5 nanometers.
3. The method according to claim 1 , wherein the gate dielectric capping layer has a material of TiN.
4. The method according to claim 1 , wherein the oxygen scavenging element layer has a thickness of 5 angstroms to 50 angstroms.
5. The method according to claim 1 , wherein the oxygen scavenging element layer has a material of Ti.
6. A method for forming a gate structure, comprising:
providing a substrate, wherein the substrate comprises a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer;
forming a gate dielectric capping layer on a surface of the substrate;
forming an etching stop layer on the gate dielectric capping layer;
forming an oxygen scavenging element layer on the etching stop layer;
forming a second work function adjustment layer on the oxygen scavenging element layer;
etching the second work function adjustment layer above the pMOSFET area until the etching stop layer is exposed;
forming a first work function adjustment layer on the surface of the substrate;
performing metal layer deposition and annealing process to fill the gate trenches with a metal layer; and
removing the metal layer outside the gate trenches.
7. The method according to claim 6 , wherein the gate dielectric capping layer has a thickness of 5 angstroms to 5 nanometers.
8. The method according to claim 6 , wherein the gate dielectric capping layer has a material of TiN.
9. The method according to claim 6 , wherein the oxygen scavenging element layer has a thickness of 5 angstroms to 50 angstroms.
10. The method according to claim 6 , wherein the oxygen scavenging element layer has a material of Ti.
11. A method for forming a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; and
forming a gate structure on a surface of the substrate, comprising:
forming a gate dielectric capping layer on the surface of the substrate;
forming an etching stop layer on the gate dielectric capping layer;
forming an oxygen scavenging element layer on the etching stop layer;
forming a first work function adjustment layer on the oxygen scavenging element layer;
etching the first work function adjustment layer above the nMOSFET area until the etching stop layer is exposed;
forming a second work function adjustment layer on the surface of the substrate;
performing metal layer deposition and annealing process to fill the gate trenches with a metal layer; and
removing the metal layer outside the gate trenches.
12. A method for forming a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; and
forming a gate structure on a surface of the substrate, comprising:
forming a gate dielectric capping layer on the surface of the substrate;
forming an etching stop layer on the gate dielectric capping layer;
forming an oxygen scavenging element layer on the etching stop layer;
forming a second work function adjustment layer on the oxygen scavenging element layer;
etching the second work function adjustment layer above the pMOSFET area until the etching stop layer is exposed;
forming a first work function adjustment layer on the surface of the substrate;
performing metal layer deposition and annealing process to fill the gate trenches with a metal layer; and
removing the metal layer outside the gate trenches.