Memory devices capable of reducing lateral movement of charges
The memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell.
1. A memory device, comprising:
a tunneling insulating layer on an active region;
a charge storage layer on the tunneling insulating layer;
a blocking insulating layer on the charge storage layer; and
a control gate electrode on the blocking insulating layer,
wherein the control gate electrode has an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode, and
wherein the control gate electrode has an inverted mesa structure having two opposing inclined surfaces each joined at one end to a bottom surface of the control gate electrode and at another end to a surface of the control gate electrode extending in a perpendicular direction to the bottom surface of the control gate electrode.
2. The device of claim 1 , wherein the central portion of the control gate electrode has a plane surface opposite the blocking insulating layer, and
the edge portion of the control gate electrode includes one of the two opposing inclined surfaces, and
the two opposing inclined surfaces are each inclined towards the blocking insulating layer.
3. The device of claim 2 , wherein the two opposing inclined surfaces are inclined towards the central portion of the control gate electrode.
4. The device of claim 2 , wherein the edge portion of the control gate electrode has a thickness equal to, or smaller than, that of the central portion thereof, and
the edge portion of the control gate electrode tapers outward towards a sidewall of the memory device and away from the blocking insulating layer.
5. The device of claim 4 , wherein the bottom surface of the control gate electrode, which faces the blocking insulating layer, is narrower than an opposite surface thereof.
6. The device of claim 1 , further comprising:
at least two of the control gate electrodes; and
a bottom spacer between the at least two control gate electrodes, wherein the bottom spacer fills a region between the edge portion of the at least two control gate electrodes and the blocking insulating layer.
7. The device of claim 1 , further comprising:
a gate dielectric material in the central portion of the memory cell corresponding to the central portion of the control gate electrode, wherein the gate dielectric material is thinner than that in an edge portion of the memory cell corresponding to the edge portion of the control gate electrode.
8. The device of claim 1 , wherein the charge storage layer is a charge trap layer.
9. The device of claim 1 , wherein the control gate electrode has another edge portion spaced farther apart from the blocking insulating layer than the central portion of the control gate electrode, and
the edge portions of the control gate electrode are on opposing sides of the control gate electrode and face the blocking insulating layer.
10. The device of claim 9 , wherein the central portion of the control gate electrode is positioned between the edge portions of the control gate electrode.