Arrangement for digital-to-analog converter
Among other things, an arrangement for a digital-to-analog converter (DAC) is provided herein. In some embodiments, a metal-oxide semiconductor (MOS) array of the DAS comprises one or more cells respectively comprising one or more current sources. The current sources comprise one or more transistors having a horizontal gate layout. A switch arrangement of the DAS, to which the MOS array is connected, comprises one or more transistors having a vertical gate layout. Accordingly, in some embodiments, a DAC is provided which comprises transistors having a vertical gate layout and transistors having a horizontal gate layout.
1. An arrangement for a digital-to-analog converter (DAC), comprising:
a current source configured to supply a current and comprising a first supply transistor, the first supply transistor comprising:
a first source;
a first drain; and
a first gate between the first source and the first drain, the first supply transistor having a horizontal gate layout; and
a switching element configured to switch a current of the current source between a first terminal and a second terminal, the switching element comprising a first switching transistor, the first switching transistor comprising:
a second source;
a second drain; and
a second gate between the second source and the second drain, the first switching transistor having a vertical gate layout, wherein a channel length of a first channel of the first supply transistor is at least three times larger than a channel length of a second channel of the first switching transistor.
2. The arrangement of claim 1 , the first terminal coupled to an analog output terminal and the second terminal coupled to ground.
3. The arrangement of claim 1 , wherein the DAC is a current-steering DAC.
4. The arrangement of claim 1 , the current source comprising a second supply transistor coupled in series with the first supply transistor, the second supply transistor having a horizontal gate layout.
5. The arrangement of claim 4 , the first source coupled to a power supply and the first drain coupled to a third source of the second supply transistor.
6. The arrangement of claim 4 , a third source of the second supply transistor coupled to the first drain and a third drain of the second supply transistor coupled to the second source.
7. The arrangement of claim 1 , the switching element comprising a second switching transistor, the second switching transistor having a vertical gate layout.
8. The arrangement of claim 1 , wherein the current source is a cascode current source.
9. A digital-to-analog converter (DAC), comprising:
a metal-oxide semiconductor (MOS) array comprising an arrangement of cells,
a first cell of the MOS array comprising:
a first current source comprising a first supply transistor having a horizontal gate layout, and
a second cell of the MOS array comprising:
a second current source comprising a second supply transistor having a horizontal gate layout;
a first switching element configured to switch a first current of the first current source between a first terminal and a second terminal, the first switching element comprising a first switching transistor having a vertical gate layout; and
a second switching element configured to switch a second current of the second current source between a third terminal and a fourth terminal, the second switching element comprising a second switching transistor having a vertical gate layout, wherein the first terminal and the third terminal define a common node, the second terminal is coupled to a first voltage source maintaining a first voltage and the fourth terminal is coupled to a second voltage source maintaining a second voltage different than the first voltage.
10. The converter of claim 9 , wherein the DAC is a current-steering DAC.
11. The converter of claim 9 , wherein the first current source is a cascode current source.
12. The converter of claim 9 , the first current source comprising a third supply transistor having a horizontal gate layout.
13. The converter of claim 12 , the first supply transistor and the third supply transistor arranged in series.
14. The converter of claim 9 , comprising a biasing circuit configured to generate a bias voltage applied to the first supply transistor.
15. The converter of claim 9 , comprising a biasing circuit configured to generate a bias voltage that facilitates setting a value of current output by the first current source.
16. The converter of claim 9 , the MOS array surrounded by a dummy MOS array.
17. The converter of claim 16 , the dummy MOS array having a surface area that is less than a surface area of a second dummy MOS array of a second MOS array, where the second MOS array comprises transistors having a vertical gate layout.
18. The converter of claim 16 , the dummy MOS array having a surface area that is less than a surface area of the MOS array.
19. The converter of claim 9 , at least one of the first supply transistor or the first switching transistor comprising a p-type transistor.
20. A current-steering digital-to-analog converter (DAC), comprising:
a metal-oxide semiconductor (MOS) array comprising a first supply MOS transistor having a horizontal-gate layout and a second supply MOS transistor having a vertical-gate layout;
a dummy MOS array surrounding the MOS array; and
a switch arrangement comprising a first switching MOS transistor coupled to the first supply MOS transistor and having a vertical-gate layout and a second switching MOS transistor coupled to the second supply MOS transistor and having a vertical-gate layout.