Bypassing memory requests to a main memory
Some embodiments include a computing device with a control circuit that handles memory requests. The control circuit checks one or more conditions to determine when a memory request should be bypassed to a main memory instead of sending the memory request to a cache memory. When the memory request should be bypassed to a main memory, the control circuit sends the memory request to the main memory. Otherwise, the control circuit sends the memory request to the cache memory.
1. A method for handling memory requests, comprising:
in a control circuit, performing operations for:
when a memory request should be bypassed to a main memory instead of sending the memory request to a cache memory, sending the memory request to the main memory;
otherwise, sending the memory request to the cache memory;
wherein the memory request should be bypassed to the main memory instead of sending the memory request to the cache memory when:
the memory request is part of a sequence of memory requests that comprises one or more other memory requests; and
the memory request and a predetermined number of the memory requests from the sequence of memory requests match a predetermined pattern.
2. The method of claim 1 , wherein the memory request should further be bypassed to the main memory instead of sending the memory request to the cache memory when:
the cache memory is to be busy.
3. The method of claim 2 , wherein the cache memory is to be busy when:
one or more mechanisms for communicating with the cache memory will not be available for use within a predetermined time.
4. The method of claim 2 , wherein, when the memory request is part of a sequence of memory requests that comprises one or more other memory requests and the memory request, the cache memory is to be busy when:
a predetermined number of the other memory requests can be completed from an input-output buffer in the cache memory without refreshing the input-output buffer in the cache memory and so the predetermined number of the other memory requests are to be sent to the cache memory before the memory request.
5. The method of claim 4 , wherein the predetermined number of the other memory requests that are to be sent to the cache memory before the memory request comprise at least one of:
one or more memory requests that occurred before the memory request; or
one or more memory requests that occurred after the memory request.
6. The method of claim 1 , wherein, when the memory request is part of a sequence of memory requests that comprises one or more other memory requests and the memory request, the memory request should further be bypassed to the main memory instead of sending the memory request to the cache memory when:
a portion of the memory requests from the sequence of memory requests including the memory request cannot be completed from an input-output buffer in the cache memory without refreshing the input-output buffer in the cache memory, but can be completed from an input-output buffer in the main memory without refreshing the input-output buffer in the main memory, and so the portion of the sequence of memory requests is to be sent to the main memory.
7. The method of claim 1 , wherein, when the memory request is part of a sequence of memory requests that comprises one or more other memory requests and the memory request, the memory request should further be bypassed to the main memory instead of sending the memory request to the cache memory when:
a predetermined number of the other memory requests are to be sent to the cache memory.
8. The method of claim 7 , wherein the predetermined number is set based on a rate of completion of memory requests by the cache memory and a rate of completion of memory requests by the main memory.
9. The method of claim 1 , wherein the predetermined pattern is a stream of sequential memory requests.
10. The method of claim 1 , wherein the memory request should further be bypassed to the main memory instead of sending the memory request to the cache memory when:
the memory request was generated by a lower-priority source.
11. The method of claim 1 , wherein:
the control circuit is a memory controller located on a processor semiconductor die;
the cache memory is located on one or more DRAM cache memory semiconductor dies that are stacked with the processor semiconductor die in a first package, the DRAM cache memory dies being communicatively coupled to the processor semiconductor die and serving as a cache for a processor on the processor semiconductor die; and
the main memory is located on one or more DRAM memory semiconductor dies in a second package that is coupled to the first package.
12. An apparatus for handling memory requests, comprising:
a control circuit, wherein the control circuit is configured to:
when a memory request should be bypassed to a main memory instead of sending the memory request to a cache memory, send the memory request to the main memory;
otherwise, send the memory request to the cache memory:
wherein the memory request should be bypassed to the main memory instead of sending the memory request to the cache memory when:
the memory request is part of a sequence of memory requests that comprises one or more other memory requests; and
the memory request and a predetermined number of the memory requests from the sequence of memory requests match a predetermined pattern.
13. The apparatus of claim 12 , wherein the control circuit is configured so that the memory request should also be bypassed to the main memory instead of sending the memory request to the cache memory when:
the cache memory is to be busy.
14. The apparatus of claim 13 , wherein the cache memory is to be busy when:
one or more mechanisms for communicating with the cache memory will not be available for use within a predetermined time.
15. The apparatus of claim 13 , wherein, when the memory request is part of a sequence of memory requests that comprises one or more other memory requests and the memory request, the cache memory is to be busy when:
a predetermined number of the other memory requests can be completed from an input-output buffer in the cache memory without refreshing the input-output buffer in the cache memory and so the predetermined number of the other memory requests are to be sent to the cache memory before the memory request.
16. The apparatus of claim 15 , wherein the predetermined number of the other memory requests that are to be sent to the cache memory before the memory request comprise at least one of:
one or more memory requests that occurred before the memory request; or
one or more memory requests that occurred after the memory request.
17. The apparatus of claim 12 , wherein, when the memory request is part of a sequence of memory requests that comprises one or more other memory requests and the memory request, the control circuit is configured so that memory request should also be bypassed to the main memory instead of sending the memory request to the cache memory when:
a portion of the memory requests from the sequence of memory requests including the memory request cannot be completed from an input-output buffer in the cache memory without refreshing the input-output buffer in the cache memory, but can be completed from an input-output buffer in the main memory without refreshing the input-output buffer in the main memory, and so the portion of the sequence of memory requests is to be sent to the main memory.
18. The apparatus of claim 12 , wherein the predetermined pattern is a stream of sequential memory requests.
19. The apparatus of claim 12 , wherein the control circuit is configured so that the memory request should also be bypassed to the main memory instead of sending the memory request to the cache memory when:
the memory request was generated by a lower-priority source.
20. The apparatus of claim 12 , further comprising:
a processor semiconductor die comprising a memory controller in a processor, wherein the control circuit is located in the memory controller;
one or more DRAM cache memory semiconductor dies stacked with the processor semiconductor die, the DRAM cache memory dies being communicatively coupled to the processor semiconductor die and serving as a cache for a processor on the processor semiconductor die;
one or more DRAM memory semiconductor dies;
a first package containing the processor semiconductor die and the DRAM cache memory dies stacked with the processor semiconductor die; and
a second package that is communicatively coupled to the first package, the second package containing the DRAM memory semiconductor dies.
21. A computer-readable storage medium storing instructions that, when executed by a computing device, cause the computing device to perform a method for handling memory requests, wherein the method comprises:
when a memory request should be bypassed to a main memory instead of sending the memory request to a cache memory, sending the memory request to the main memory;
otherwise, sending the memory request to the cache memory;
wherein the memory request should be bypassed to the main memory instead of sending the memory request to the cache memory when:
the memory request is part of a sequence of memory requests that comprises one or more other memory requests; and
the memory request and a predetermined number of the memory requests from the sequence of memory requests match a predetermined pattern.