IP Library Granted Patent US 8,745,563
Granted Patent B2
US 8,745,563 · App. 13/710,145 · Granted Jun 3, 2014

Computationally efficient modeling and simulation of large scale systems

Inventors: Jitesh Jain (Rajasthan, IN); Stephen F Cauley (West Lafayette, IN); Hong Li (He nan, CN); Cheng-Kok Koh (West Lafayette, IN); Vankataramanan Balakrishnan (West Lafayette, IN)
Assignee: Purdue Research Foundation
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Quick Facts
Patent No.
US 8,745,563
App. No.
13/710,145
Granted
Jun 3, 2014
Kind
B2
Abstract

A system for simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof, including a processor, and a memory, the processor configured to perform obtaining a matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure, the element values for each matrix including inductance L and inverse capacitance P, obtaining an adjacency matrix A associated with the interconnect structure, storing the matrices X, Y, and A in the memory, and performing numerical integration to solve first and second equations.

Claims (138)

1. A system for simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof, comprising:

a processor; and

a memory, said processor configured to:

obtaining a matrix X and a matrix Y containing different combinations of passive circuit element values for said interconnect structure, said element values for each matrix including inductance L and inverse capacitance P,

obtaining an adjacency matrix A associated with said interconnect structure,

storing said matrices X, Y, and A in said memory, and

performing numerical integration to solve first and second equations each including as a factor product of inverse said matrix X (X −1 ) and at least one other matrix, said first equation including X −1 Y, X −1 A, and X −1 P, and said second equation including X −1 A and X −1 P.

2. The system of claim 1 , wherein said matrices X and Y each contain resistance values in addition to L and P.

3. The system of claim 2 , wherein said first equation is substantially of the form,

i

l

k

+

1

=

X

-

1

Y

i

l

k

+

X

-

1

A

v

n

k

+

h

4

X

-

1

A

P

(

I

s

k

+

1

+

I

s

k

)

,

where v n and i l are node voltages and inductor currents, respectively, A is an adjacency matrix for the circuit, and I s is a current source vector, and wherein said second equation is substantially of the form

X

-

1

A

v

n

k

+

1

=

X

-

1

A

v

n

k

-

h

2

X

-

1

A

P

A

T

(

i

l

k

+

1

+

i

l

k

)

+

h

2

X

-

1

A

P

(

I

s

k

+

1

+

I

s

k

)

.

Assignments (1)
CONFIRMATORY LICENSE Recorded Jul 16, 2014
From: PURDUE UNIVERSITY
To: NATIONAL SCIENCE FOUNDATION
Reel/Frame 033344/0481 →
Continuity (2)
Continuation 12852942 · Aug 9, 2010
Related Publication 20130124168A1 · May 16, 2013