Semiconductor device with high breakdown voltage and manufacture thereof
View Patent ↗A semiconductor device includes: first and second n-type wells formed in p-type semiconductor substrate, the second n-type well being deeper than the first n-type well; first and second p-type backgate regions formed in the first and second n-type wells; first and second n-type source regions formed in the first and second p-type backgate regions; first and second n-type drain regions formed in the first and second n-type wells, at positions opposed to the first and second n-type source regions, sandwiching the first and the second p-type backgate regions; and field insulation films formed on the substrate, at positions between the first and second p-type backgate regions and the first and second n-type drain regions; whereby first transistor is formed in the first n-type well, and second transistor is formed in the second n-type well with a higher reverse voltage durability than the first transistor.
1. A semiconductor device comprising:
a p-type semiconductor substrate;
a first n-type well formed in the p-type semiconductor substrate with a first depth from a surface of the p-type semiconductor substrate;
a second n-type well formed in the p-type semiconductor substrate with a second depth from the surface of the p-type semiconductor substrate, the second depth being smaller than the first depth;
a first and a second p-type backgate regions formed in the first and the second n-type wells, respectively;
a first and a second n-type source regions formed in the first and the second p-type backgate regions, respectively;
a first and a second n-type drain regions formed in the first and the second n-type wells, respectively, at positions opposing to the first and the second n-type source regions, with the first and the second p-type backgate regions located in between; and
field insulation films formed on the p-type semiconductor substrate, at positions between the first and the second p-type backgate regions and the first and the second n-type drain regions, respectively;
wherein a first transistor with a low reverse voltage durability is formed in the first n-type well and a second transistor with a reverse voltage durability higher than that of the first transistor is formed in the second n-type well.
2. A semiconductor device as defined in claim 1 , wherein the first transistor has a smaller in-plane area than that of the second transistor.
3. A semiconductor device as defined in claim 1 , further comprising a first Zener diode which includes:
a third n-type well formed with substantially same depth from the surface of the p-type semiconductor substrate and substantially same impurity concentration distribution as those of the second n-type well;
a first p-type anode region formed in the third n-type well with substantially same depth and impurity concentration distribution as those of the second p-type backgate region; and
a first n-type cathode region formed in the first p-type anode region with substantially same depth and impurity concentration distribution as those of the second source region.
4. A semiconductor device as defined in claim 3 , further comprising a second Zener diode which includes:
a fourth n-type well formed with substantially same depth from the surface of the p-type semiconductor substrate and substantially same impurity concentration distribution as those of the first n-type well;
a second p-type anode region formed in the fourth n-type well with substantially the same depth and impurity concentration distribution as those of the first p-type backgate region; and
a second n-type cathode region formed in the second p-type anode region with substantially same depth and impurity concentration distribution as those of the first source region.
5. A CAN system including a plurality of communications modules, and a reverse current blocking circuit, the reverse current blocking circuit comprising:
a p-type semiconductor substrate;
a first n-type well formed in the p-type semiconductor substrate with a first depth from a surface of the p-type semiconductor substrate;
a second n-type well formed in the p-type semiconductor substrate with a second depth from the surface of the p-type semiconductor substrate, the second depth being smaller than the first depth;
a first and a second p-type backgate regions formed in the first and the second n-type wells, respectively;
a first and a second n-type source regions formed in the first and the second p-type backgate regions, respectively;
a first and a second n-type drain region formed in the first and the second n-type wells, respectively, at positions opposing to the first and the second n-type source regions, with the first and the second p-type backgate regions located in between; and
field insulation films formed on the p-type semiconductor substrate, at positions between the first and the second p-type backgate regions and the first and the second n-type drain regions, respectively;
wherein a first transistor with a reverse voltage durability is formed in the first n-type well and a second transistor with a reverse voltage durability lower than that of the first transistor is formed in the second n-type well.