IP Library Granted Patent US 9,034,769
Granted Patent B2
US 9,034,769 · App. 13/712,699 · Granted May 19, 2015

Methods of selectively removing a substrate material

Inventors: Mark A. Bossler (Meridian, ID); Jaspreet S. Gandhi (Boise, ID); Christopher J. Gambee (Caldwell, ID); Randall S. Parker (Boise, ID)
Assignee: Micron Technology, Inc.
H01L23/5384H01L21/30604H01L2924/0002H01L21/02068H01L21/02238H01L21/3065
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Quick Facts
Patent No.
US 9,034,769
App. No.
13/712,699
Granted
May 19, 2015
Kind
B2
Abstract

A method for selective removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SF 6 without forming copper sulfide on the at least one copper feature. Additional methods are also disclosed, as well as semiconductor structures produced from such methods.

Claims (23)

1. A method for selectively removing substrate material, the method comprising:

oxidizing a semiconductor structure comprising a substrate and at least one copper feature to form a copper oxide material on the at least one copper feature; and

removing a portion of the substrate using an etchant comprising sulfur hexafluoride (SF 6 ) without forming copper sulfide on the at least one copper feature and without removing the copper oxide material on the at least one copper feature.

2. The method of claim 1 , wherein oxidizing a semiconductor structure comprises exposing the semiconductor structure to a plasma selected from the group consisting of an oxygen plasma and an ozone plasma.

3. The method of claim 1 , wherein oxidizing a semiconductor structure comprises exposing the semiconductor structure to a hydrogen peroxide solution.

4. The method of claim 1 , wherein oxidizing a semiconductor structure comprising a substrate and at least one copper feature comprises oxidizing a silicon-containing substrate and the at least one copper feature to form a silicon oxide material on exposed portions of the silicon-containing substrate and the copper oxide material on exposed portions of the at least one copper feature.

5. A method for selectively removing material from a substrate, the method comprising:

subjecting a semiconductor structure comprising a substrate, at least one copper feature, and an insulating component between the substrate and the at least one copper feature to an oxidizing agent to form a silicon oxide material on the substrate and a copper oxide material on the at least one copper feature;

removing the silicon oxide material to expose the substrate; and

removing at least a portion of the substrate using a SF 6 -containing etchant without removing the copper oxide material and the insulating component.

6. The method of claim 5 , wherein the insulating component comprises an insulating material.

7. The method of claim 6 , wherein the insulating component further comprises a diffusion barrier material.

8. The method of claim 5 , wherein the at least one copper feature comprises at least one through-silicon via filled with copper.

9. A method for selectively removing material from a substrate, the method comprising:

exposing a semiconductor structure comprising a silicon-containing material, at least one copper-filled through-substrate via and an insulating material and a diffusion barrier material between the silicon-containing material and copper of the at least one copper-filled through-substrate via to an oxidizing agent to form a copper oxide material on the at least one copper-filled through-substrate via;

selectively removing a portion of the silicon-containing material with a SF 6 -containing etchant to form the at least one copper-filled through-substrate via extending above a surface of the silicon-containing material; and

after selectively removing a portion of the silicon-containing material with a SF 6 -containing etchant, removing the copper oxide material.

10. The method of claim 9 , wherein selectively removing a portion of the silicon-containing material with a SF 6 -containing etchant comprises etching the portion of the silicon-containing material without substantially etching the copper oxide material, the insulating material, and the diffusion barrier material.

11. The method of claim 9 , wherein exposing a semiconductor structure comprising a silicon-containing material, an insulating material, a diffusion barrier material, and at least one copper-filled through-substrate via to an oxidizing agent comprises oxidizing the silicon-containing material and the copper with a plasma comprising the oxidizing agent.

12. The method of claim 9 , further comprising, before selectively removing a portion of the silicon-containing material with a SF 6 -containing etchant, removing an oxide material on a surface of the silicon-containing material.

13. The method of claim 9 , wherein selectively removing a portion of the silicon-containing material with a SF 6 -containing etchant comprises removing from about 2 microns to about 10 microns of the silicon-containing material.

14. The method of claim 9 , wherein exposing a semiconductor structure comprising a silicon-containing material, an insulating material, a diffusion barrier material, and at least one copper-filled through-substrate via to an oxidizing agent comprises exposing the silicon-containing material and the at least one copper-filled through-substrate via to an O 2 plasma.

15. The method of claim 9 , wherein selectively removing a portion of the silicon-containing material with a SF 6 -containing etchant to form the at least one copper-filled through-substrate via extending above a surface of the silicon-containing material comprises recessing an upper surface of the silicon-containing material.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2012
From: BOSSLER, MARK A.; GANDHI, JASPREET S.; GAMBEE, CHRISTOPHER J.; PARKER, RANDALL S.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 029456/0560 →
Continuity (1)
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