Semiconductor device with silicon-containing hard mask and method for fabricating the same
A semiconductor device includes a semiconductor substrate having an etch target layer provided on the surface thereof, and a hard mask layer formed over the etch target layer and including silicon, wherein the hard mask layer includes a dual structure including a first area and a second area having a larger etch rate than the first area, in order to increase an etching selectivity of the hard mask layer.
1. A method for fabricating a semiconductor device, comprising:
forming an etch target layer over a semiconductor substrate;
forming a silicon-containing layer over the etch target layer, the silicon-containing layer comprising a first area and a second area formed over the first area and having a smaller etch rate than the first area;
patterning the silicon-containing layer; and
etching the etch target layer using the patterned silicon-containing layer as an etch barrier,
wherein a portion of the etch target layer is etched by using the first area and the second area as the etch barrier and a rest portion of the etch target layer is etched by using only the second area as the etch barrier.
2. The method of claim 1 , wherein, in the forming of the silicon-containing layer,
the second area comprises an impurity, and the first area is undoped.
3. The method of claim 2 , wherein the impurity comprises boron.
4. The method of claim 1 , wherein the forming of the silicon-containing layer comprises:
forming an undoped silicon-containing layer as the first area; and
forming a doped silicon-containing layer as the second area over the undoped silicon-containing layer, while in-situ doping an impurity.
5. The method of claim 1 , wherein the forming of the silicon-containing layer comprises:
forming an undoped silicon-containing layer as the first area; and
forming the second area by doping an impurity into an upper portion of the undoped silicon-containing layer.
6. A method for fabricating a semiconductor device, comprising:
forming an insulation layer over a semiconductor substrate;
forming a polysilicon layer pattern over the insulation layer, the polysilicon layer pattern having an undoped area and a doped area formed over the undoped area; and
forming a pattern by etching the insulation layer by using the polysilicon layer pattern as an etch barrier,
wherein a portion of the insulation layer is etched by using the undoped area and the doped area as the etch barrier and a rest portion of the insulation layer is etched by using only the undoped area as the etch barrier.
7. The method of claim 6 , wherein, in the forming of the polysilicon layer pattern, the doped area is formed by doping boron.
8. The method of claim 7 , wherein the doping concentration of boron has a range of about 1×10 17 atoms/cm 3 to 1×10 18 atoms/cm 3 .
9. The method of claim 6 , wherein the forming of the polysilicon layer pattern comprises:
forming an undoped polysilicon layer as the undoped area;
forming a boron-doped polysilicon layer as the doped area over the undoped polysilicon layer, while in-situ doping boron;
forming a carbon-containing pattern over the boron-doped polysilicon layer; and
etching the boron-doped polysilicon layer and the undoped polysilicon layer using the carbon-containing pattern as an etch barrier.
10. The method of claim 9 , wherein the carbon-containing pattern comprises amorphous carbon.
11. The method of claim 6 , wherein the forming of the polysilicon layer pattern comprises:
forming an undoped polysilicon layer as the undoped area;
forming a boron-doped polysilicon layer as the doped area by doping boron into an upper portion of the undoped polysilicon layer;
forming a carbon-containing pattern over the boron-doped polysilicon layer; and
etching the boron-doped polysilicon layer and the undoped polysilicon layer using the carbon-containing pattern as an etch barrier.
12. The method of claim 6 , wherein the doped area is formed to such a small thickness as to be removed at the same time when the insulation layer is completely etched.
13. The method of claim 6 , wherein the doped area is formed to a smaller thickness than the undoped area.
14. The method of claim 6 , further comprising removing the polysilicon layer pattern through wet etching, after the etching of the insulation layer.
15. The method of claim 6 , wherein the insulation layer comprise an oxide layer, a nitride layer, a plurality of oxide layers, a stacked structure of oxide and nitride layers, or a structure in which a plurality of oxides and nitrides are alternately stacked.
16. The method of claim 6 , further comprising, after the forming of the pattern:
forming a storage node in the pattern; and
removing the insulation layer.