Verification module apparatus for debugging software and timing of an embedded processor design that exceeds the capacity of a single FPGA
View Patent ↗A plurality of Field Programmable Gate Arrays (FPGA), high performance transceivers, and memory devices provide a verification module for timing and state debugging of electronic circuit designs. Signal value compression circuits and gigabit transceivers embedded in each FPGA increase the fanout of each FPGA. Ethernet communication ports enable remote software debugging of processor instructions.
1. A system for designing and emulating an embedded processor design, which system comprises:
(i) a verification module and system controller comprising:
(a) an interface to a user workstation;
(b) at least one field programmable logic device configured as an conventional embedded logic analyzer IP circuit description;
(c) at least one first clock and user signal compression tunnel portal;
(d) a plurality of gigabit transceivers; and
(ii) at least one system on chip (SoC) partition logic module coupled to the first clock; and user signal logic value compression tunnel portal of the verification module, each SoC partition logic module comprising:
(e) a plurality of field programmable logic devices for emulating the user design wherein each field programmable logic device comprises, in addition to the user design, a circuit for a user signal compression tunnel, the circuit for a user signal compression tunnel coupled to at least one second clock and user signal compression tunnel portal, whereby a portion of the user design assigned to the programmable logic device communicates with portions of the user design assigned to other programmable logic devices through gigabit transceivers; and
(f) at least one field programmable logic device configured as a processor coupled by a circuit for user signal compression tunnel portal to each other field programmable logic device, whereby monitoring all on-board global clocks in real time, monitoring and displaying voltage, current and temperature; setting external I/O voltages through software, and global reset is provided remotely through software.
2. A system as in claim 1 , wherein the clock and user signal compression tunnel portal comprises: a controller for clock signals, and gigabit transceiver backplane functional blocks.
3. A system as in claim 1 , wherein the clock and user signal compression tunnel portal comprises:
a controller for clock signals, and
a gigabit transceiver optical interface circuit.
4. A system as in claim 1 , wherein each circuit for a user signal compression tunnel
compares signal values to signal logic values previously written into memory devices; and
writes new signal logic values into DDR3 memory devices.
5. A system as in claim 4 , wherein each circuit for a user signal compression tunnel transfers to the user signal compression tunnel portal only addresses of memory stored logic values when signal logic values match stored signal logic values.
6. A system as in claim 1 , wherein each circuit for a user signal compression tunnel transfers to the user signal compression tunnel portal both a new signal value and an address in memory devices at which the new signal value shall be stored.
7. A system as in claim 1 , wherein the verification module further comprises:
memory devices for user signal logic value compression, said storage communicatively coupled to a field programmable logic device containing an embedded logic analyzer.