NAND COMMAND AGGREGATION
An embodiment is a method and apparatus to provide an optimization of commands in a flash device. Commands sent by at least a top-level processor to a flash device are buffered in a buffer. The buffered commands are analyzed for an optimizing condition. The commands are aggregated if the optimizing condition is met. The aggregated commands are sent to the flash device.
1 . A method comprising:
buffering commands sent by at least a top-level processor to a flash device in a buffer;
analyzing the buffered commands for an optimizing condition;
aggregating the commands if the optimizing condition is met; and
sending the aggregated commands to the flash device.
2 . The method of claim 1 wherein buffering commands comprises:
buffering commands sent by at least one of a host domain manager, a garbage collector, and a wear-level controller.
3 . The method of claim 1 wherein analyzing the commands comprises:
checking a destination condition to the flash device as the optimizing condition.
4 . The method of claim 3 wherein aggregating the commands comprises:
combining commands having same destination condition.
5 . The method of claim 4 wherein the same destination condition corresponds to adjacent blocks or multiple planes in the flash device.
6 . The method of claim 1 wherein analyzing the commands further comprises:
analyzing dependency in the commands.
7 . The method of claim 1 wherein the commands correspond to one of a write, a read, and an erase command.
8 . A circuit comprising:
a buffer to buffer commands sent by at least a top-level processor to a flash device;
an analyzer coupled to the buffer to analyze the buffered commands for an optimizing condition;
an aggregator coupled to the analyzer to aggregate the commands if the optimizing condition is met; and
an interface to send the aggregated commands to the flash device.
9 . The circuit of claim 8 wherein the buffer buffers commands sent by at least one of a host domain manager, a garbage collector, and a wear-level controller.
10 . The circuit of claim 8 wherein the analyzer checks a destination condition to the flash device as the optimizing condition.
11 . The circuit of claim 10 wherein the aggregator combines commands having same destination condition.
12 . The circuit of claim 11 wherein the same destination condition corresponds to adjacent blocks or multiple planes in the flash device.
13 . The circuit of claim 8 wherein the analyzer further analyzes dependency in the commands.
14 . The circuit of claim 8 wherein the commands correspond to one of a write, a read, and an erase command.
15 . A system comprising:
a plurality of top-level processors;
a flash device; and
a flash domain manager coupled to the plurality of top-level processors and the flash device to optimize commands sent by at least one of the top-level processors to the flash device, the flash domain manager comprising:
a buffer to buffer the commands,
an analyzer coupled to the buffer to analyze the buffered commands for an optimizing condition;
an aggregator coupled to the analyzer to aggregate the commands if the optimizing condition is met; and
an interface to send the aggregated commands to the flash device.
16 . The system of claim 15 wherein one of the top-level processors is one of a host domain manager, a garbage collector, and a wear-level controller.
17 . The system of claim 15 wherein the analyzer checks a destination condition to the flash device as the optimizing condition.
18 . The system of claim 17 wherein the aggregator combines commands having same destination condition.
19 . The system of claim 18 wherein the same destination condition corresponds to adjacent blocks or multiple planes in the flash device.
20 . The system of claim 15 wherein the analyzer further analyzes dependency in the commands.
21 . The system of claim 15 wherein the commands correspond to one of a write, a read, and an erase command.