Network interface with logging
View Patent ↗Structures and methods for improving logging in network structures are disclosed herein. In one embodiment, an apparatus can include: (i) a network interface card (NIC) configured to receive data, to transmit data, and to send data for logging; (ii) a memory log coupled to the NIC, where the memory log comprises non-volatile memory (NVM) configured to write the data sent for logging from the NIC; and (iii) where the data being sent for logging by the memory log occurs substantially simultaneously with the data being received by the NIC, and the data being transmitted from the NIC.
1. An apparatus, comprising:
a) a network interface card (NIC) configured to receive data, to transmit data, and to send data for logging;
b) a memory log coupled to the NIC, wherein the memory log comprises resistive switching non-volatile memory (NVM) configured to write the data sent for logging from the NIC; and
c) wherein the data being sent by the NIC for logging in the memory log occurs to at least partially overlap operations with the data being received by the NIC, and the data being transmitted from the NIC, and wherein initiation of the data being sent by the NIC for logging in the memory log occurs prior to initiation of the data being transmitted from the NIC.
2. The apparatus of claim 1 , wherein the NIC is configured to begin transmit of the data while the memory log writes the data for logging from the NIC.
3. The apparatus of claim 1 , wherein the memory log and the NIC are integrated on a same network card.
4. The apparatus of claim 3 , wherein the memory log and the NIC are integrated on a same chip in the network card.
5. The apparatus of claim 1 , wherein the data received by the NIC comprises a peripheral component interconnect express (PCIe) standard, and the data transmitted from the MC comprises an Ethernet standard.
6. The apparatus of claim 1 , further comprising a bridge coupled between the NIC and the memory log.
7. The apparatus of claim 1 , wherein the resistive switching NVM comprises a conductive bridging random-access memory (CBRAM) having a plurality of memory cells.
8. The apparatus of claim 7 , wherein each of the plurality of memory cells comprises:
a) a programmable impedance element having an inert electrode, and an active electrode that is coupled to a bit line; and
b) a transistor having a drain coupled to the inert electrode a gate coupled to a word line, and a source coupled to a source line.
9. The apparatus of claim 8 , wherein the programmable impedance element comprises:
a) the inert electrode coupled to a first side of a solid electrolyte;
b) the active electrode coupled to a second side of the solid electrolyte, wherein the programmable impedance element is programmed by formation of a conductive path between the active and inert electrodes; and
c) a plurality of mobile elements derived from the active electrode, wherein the plurality of mobile elements are reduced in the solid electrolyte to form the conductive path.
10. The apparatus of claim 9 , wherein:
a) the conductive path in the programmable impedance element is formed by application of a first voltage across the active and inert electrodes, the conductive path substantially remaining once formed after the first voltage is removed; and
b) at least a portion of the conductive path is dissolved to erase the programmable impedance element by application of a second voltage across the active and inert electrodes.
11. An apparatus, comprising:
a) a peripheral component interconnect express (PCIe) bridge configured to receive data, to resend the data, and to send data for logging;
b) a PCIe device configured to receive the data that is resent from the PCIe bridge;
c) a memory log coupled to the PCIe bridge, wherein the memory log comprises resistive switching non-volatile memory (NVM) configured to write the data sent for logging from the PCIe bridge; and
d) wherein the data being sent by the PCIe bridge for logging in the memory log occurs to at least partially overlap operations with the data being received by the PCIe bridge, and the data being resent from the PCIe bridge, and wherein initiation of the data being sent by the PCIe bridge for logging in the memory log occurs prior to initiation of the data being transmitted from the PCIe bridge.
12. The apparatus of claim 11 , wherein the PCIe device is configured to begin receiving the resend data while the memory log writes the data for logging from the PCIe bridge.
13. The apparatus of claim 11 , wherein the PCIe bridge is configured to receive the data on a first PCIe bus, and to resend the data on a second PCIe bus.
14. The apparatus of claim 11 , wherein the resistive switching NVM comprises a conductive bridging random-access memory (CBRAM) having a plurality of memory cells.
15. The apparatus of claim 14 , wherein each of the plurality of memory cells comprises:
a) a programmable impedance element having an inert electrode, and an active electrode that is coupled to a bit line; and
b) a transistor having a drain coupled to the inert electrode a gate coupled to a word line, and a source coupled to a source line.
16. The apparatus of claim 15 , wherein the programmable impedance element comprises:
a) the inert electrode coupled to a first side of a solid electrolyte;
b) the active electrode coupled to a second side of the solid electrolyte, wherein the programmable impedance element is programmed by formation of a conductive path between the active and inert electrodes; and
c) a plurality of mobile elements derived from the active electrode, wherein the plurality of mobile elements are reduced in the solid electrolyte to form the conductive path.
17. The apparatus of claim 16 , wherein:
a) the conductive path in the programmable impedance element is formed by application of a first voltage across the active and inert electrodes, the conductive path substantially remaining once formed after the first voltage is removed; and
b) at least a portion of the conductive path is dissolved to erase the programmable impedance element by application of a second voltage across the active and inert electrodes.
18. A method, comprising:
a) receiving data in a network interface card (NIC);
b) logging data from the NIC by writing data in a memory log, wherein the memory log comprises resistive switching non-volatile memory (NVM) for writing the data for logging from the NIC; and
c) transmitting data from the NIC, wherein the data is received by the NIC, the data is transmitted from the NIC, and the data is written for logging in the memory log to at least partially overlap operations, wherein initiation of the data being sent by the NIC for logging in the memory log occurs prior to initiation of the data being transmitted from the NIC.
19. The method of claim 18 , wherein the NIC begins transmitting the data while the memory log is writing the data for logging from the NIC.
20. The method of claim 18 , wherein the memory log and the NIC are integrated on a same network card.