Semiconductor device and method for manufacturing the same
View Patent ↗A bottom-gate transistor with a short channel length and a method for manufacturing the transistor are provided. A bottom-gate transistor with a short channel length in which portions of a source electrode and a drain electrode which are proximate to a channel formation region are thinner than other portions thereof was devised. In addition, the portions of the source electrode and the drain electrode which are proximate to the channel formation region are formed in a later step than the other portions thereof, whereby a bottom-gate transistor with a short channel length can be manufactured.
1. A method for manufacturing a semiconductor device, comprising the steps of:
forming a gate electrode layer;
forming a gate insulating layer over the gate electrode layer;
forming a semiconductor layer over the gate insulating layer;
forming a first conductive layer over the semiconductor layer;
forming a second conductive layer over the first conductive layer so that the first conductive layer is exposed in a region which overlaps with a channel formation region of the semiconductor layer;
forming a protective layer over the second conductive layer;
forming a hard mask layer over the protective layer;
forming a resist pattern over the hard mask layer, the resist pattern including an opening which overlaps with the semiconductor layer;
etching the hard mask layer using the resist pattern;
etching the protective layer using the hard mask layer; and
etching the first conductive layer using the hard mask layer.
2. The method for manufacturing the semiconductor device according to claim 1 ,
wherein the semiconductor layer includes an oxide including indium and zinc.
3. The method for manufacturing the semiconductor device according to claim 1 , wherein the opening in the resist pattern is formed by an electron beam.
4. The method for manufacturing the semiconductor device according to claim 1 , wherein the hard mask layer comprises amorphous silicon.
5. The method for manufacturing the semiconductor device according to claim 1 , wherein a channel length of a transistor including the semiconductor layer is greater than or equal to 20 nm and less than or equal to 100 nm.
6. The method for manufacturing the semiconductor device according to claim 1 , wherein a length of the semiconductor layer in a channel length direction is larger than a length of the gate electrode layer in the channel length direction.
7. The method for manufacturing the semiconductor device according to claim 1 , further comprising the step of planarizing the gate insulating layer before forming the semiconductor layer.
8. The method for manufacturing the semiconductor device according to claim 1 , further comprising the step of planarizing the protective layer before forming the hard mask layer.
9. A method for manufacturing a semiconductor device, comprising the steps of:
forming a gate electrode layer;
forming a gate insulating layer over the gate electrode layer;
forming a semiconductor layer over the gate insulating layer;
forming a first conductive layer over the semiconductor layer;
forming a second conductive layer over the first conductive layer;
forming a protective layer over the second conductive layer;
forming a first resist pattern over the protective layer, the first resist pattern including a first opening;
etching the protective layer and the second conductive layer using the first resist pattern;
forming, after the step of etching, a second resist pattern over the first conductive layer and the protective layer, the second resist pattern including a second opening in a region which overlaps with the semiconductor layer; and
etching the first conductive layer using the second resist pattern.
10. The method for manufacturing the semiconductor device according to claim 9 ,
wherein the semiconductor layer includes an oxide including indium and zinc.
11. The method for manufacturing the semiconductor device according to claim 9 , wherein the second opening is formed by an electron beam.
12. The method for manufacturing the semiconductor device according to claim 9 , wherein a channel length of a transistor including the semiconductor layer is greater than or equal to 20 nm and less than or equal to 100 nm.
13. The method for manufacturing the semiconductor device according to claim 9 , wherein a length of the semiconductor layer in a channel length direction is larger than a length of the gate electrode layer in the channel length direction.
14. The method for manufacturing the semiconductor device according to claim 9 , further comprising the step of planarizing the gate insulating layer before forming the semiconductor layer.
15. A method for manufacturing a semiconductor device, comprising the steps of:
forming an oxide semiconductor layer;
forming a first conductive layer over the oxide semiconductor layer;
forming a second conductive layer over the first conductive layer so that the first conductive layer is exposed in a region which overlaps with a channel formation region of the oxide semiconductor layer;
forming a protective layer over the second conductive layer;
forming a hard mask layer over the protective layer;
forming a resist pattern over the hard mask layer, the resist pattern including an opening which overlaps with the oxide semiconductor layer;
etching the hard mask layer using the resist pattern;
etching the protective layer using the hard mask layer; and
etching the first conductive layer using the hard mask layer.
16. The method for manufacturing the semiconductor device according to claim 15 ,
wherein the oxide semiconductor layer includes indium and zinc.
17. The method for manufacturing the semiconductor device according to claim 15 , wherein the opening in the resist pattern is formed by an electron beam.
18. The method for manufacturing the semiconductor device according to claim 15 , wherein the hard mask layer comprises amorphous silicon.
19. The method for manufacturing the semiconductor device according to claim 15 , wherein a channel length of a transistor including the oxide semiconductor layer is greater than or equal to 20 nm and less than or equal to 100 nm.
20. The method for manufacturing the semiconductor device according to claim 15 , further comprising the step of planarizing the protective layer before forming the hard mask layer.