Metal oxide TFT with improved temperature stability
A metal oxide thin film transistor includes a metal oxide semiconductor channel with the metal oxide semiconductor having a conduction band with a first energy level. The transistor further includes a layer of passivation material covering at least a portion of the metal oxide semiconductor channel. The passivation material has a conduction band with a second energy level equal to, or less than 0.5 eV above the first energy level.
1. A metal oxide thin film transistor comprising:
a metal oxide semiconductor layer having a metal oxide semiconductor channel defined therein, the metal oxide semiconductor layer having a conduction band with a first energy level; and
a layer of passivation material covering at least a portion of the metal oxide semiconductor channel, the passivation material having a conduction band with a second energy level, the second energy level being equal to, or less than 0.5 eV above the first energy level, such that a barrier between the metal oxide semiconductor channel and the passivation layer is reduced allowing carriers to be drained off into the passivation layer.
2. A metal oxide thin film transistor as claimed in claim 1 wherein the passivation material includes one of Ta 2 O 5 , TiO 2 , V 2 O 5 , Nb 2 O 5 , W 2 O 3 , ZrO 2 , HfO 2 , Sc 2 O 3 , Y 2 O 3 , La 2 O 3 , Ga 2 O 3 , MgO or combinations thereof.
3. A metal oxide thin film transistor as claimed in claim 1 wherein the passivation material is substantially more insulating or less conductive than the metal oxide semiconductor layer and has a conductivity less than 10 −10 S/cm.
4. A metal oxide thin film transistor as claimed in claim 3 wherein a ratio of the metal oxide semiconductor layer conduction to the conduction of the passivation layer remains relatively constant, whereby a current switching ratio of the transistor remains relatively constant.
5. A metal oxide thin film transistor comprising:
a substrate;
a gate supported by the substrate;
a layer of gate dielectric covering at least a portion of the gate;
a metal oxide semiconductor channel positioned on the layer of gate dielectric in overlying relationship to the gate, the metal oxide semiconductor channel having a conduction band with a first energy level;
metal source/drain contacts positioned on the metal oxide semiconductor channel on opposite sides of the gate; and
a layer of passivation material covering at least a portion of the metal oxide semiconductor channel between the source/drain contacts, the passivation material having a conduction band with a second energy level, the second energy level being equal to, or less than 0.5 eV above the first energy level, such that a barrier between the metal oxide semiconductor channel and the passivation layer is reduced allowing carriers to be drained off into the passivation layer.
6. A metal oxide thin film transistor as claimed in claim 5 wherein the passivation material includes one of Ta 2 O 5 , TiO 2 , V 2 O 5 , Nb 2 O 5 , W 2 O 3 , ZrO 2 , HfO 2 , Sc 2 O 3 , Y 2 O 3 , La 2 O 3 , Ga 2 O 3 , MgO or combinations thereof.
7. A metal oxide thin film transistor as claimed in claim 6 wherein the passivation material is substantially more insulating or less conductive than the metal oxide semiconductor channel and has a conductivity less than 10 −10 S/cm.
8. A metal oxide thin film transistor as claimed in claim 7 wherein a ratio of a conduction of the metal oxide semiconductor channel to the conduction of the passivation layer remains relatively constant, whereby a current switching ratio of the transistor remains relatively constant.
9. A method of fabricating a metal oxide thin film transistor with improved temperature stability comprising, not necessarily in the order listed, the steps of:
providing a substrate and forming a gate with a layer of gate dielectric covering at least a portion of the gate;
depositing a metal oxide semiconductor layer on the gate dielectric opposite the gate, the metal oxide semiconductor layer having a conduction band with a first energy level;
positioning spaced apart source and drain contacts on the metal oxide semiconductor layer and on opposite sides of the gate, the source and drain contacts defining a channel area in the metal oxide semiconductor layer between the spaced apart source and drain contacts and in substantial alignment with the gate; and
positioning a layer of passivation material on the metal oxide semiconductor channel area, the passivation material having a conduction band with a second energy level, the second energy level being equal to, or less than 0.5 eV above the first energy level, such that a barrier between the metal oxide semiconductor channel and the passivation layer is reduced allowing carriers to be drained off into the passivation layer.
10. A method as claimed in claim 9 wherein the step of positioning the layer of passivation material includes vacuum deposition methods.
11. A method as claimed in claim 10 wherein the step of positioning the layer of passivation material by vacuum deposition methods includes one of thermal deposition, sputter deposition, CVD, and spray pyrolysis.
12. A method as claimed in claim 9 wherein the step of positioning the layer of passivation material includes patterning by one of lithography processes.
13. A method as claimed in claim 9 wherein the step of positioning the layer of passivation material includes selecting a passivation material including one of Ta 2 O 5 , TiO 2 , V 2 O 5 , Nb 2 O 5 , W 2 O 3 , ZrO 2 , HfO 2 , Sc 2 O 3 , Y 2 O 3 , La 2 O 3 , Ga 2 O 3 , MgO or combinations thereof.
14. A method as claimed in claim 9 wherein the step of positioning a layer of passivation material includes selecting a passivation material substantially more insulating or less conductive than the metal oxide semiconductor layer and having conductivity less than 10 −10 S/cm.
15. A method as claimed in claim 14 wherein the steps of depositing a metal oxide semiconductor layer and positioning a layer of passivation material includes selecting the metal oxide and the passivation material so that a ratio of the metal oxide semiconductor conduction to the conduction of the passivation material remains relatively constant, whereby a current switching ratio of the transistor remains relatively constant.
16. A method as claimed in claim 9 wherein the step of positioning the layer of passivation material is performed one of before the step of positioning the spaced apart source and drain contacts and after the step of positioning the spaced apart source and drain contacts.