Semiconductor chips having improved solidity, semiconductor packages including the same and methods of fabricating the same
View Patent ↗Semiconductor chips are provided. The semiconductor chip includes a semiconductor chip body having an arch-shaped groove in a backside thereof and a non-conductive material pattern filling the arch-shaped groove. Related methods are also provided.
1. A semiconductor chip comprising:
a semiconductor chip body having an arch-shaped groove in a backside thereof; and
a non-conductive material pattern filling the arch-shaped groove,
wherein a surface of the non-conductive material pattern is coplanar with a bottom surface of the semiconductor chip body.
2. The semiconductor chip of claim 1 , wherein the non-conductive material pattern is a material having a solidity which is greater than that of the semiconductor chip body.
3. The semiconductor chip of claim 1 , wherein the non-conductive material pattern has an adhesive property.
4. The semiconductor chip of claim 1 , wherein the non-conductive material pattern includes an epoxy type polymer material or a silicon resin material.
5. The semiconductor chip of claim 1 , wherein the non-conductive material pattern comprises a material having substantially the same grinding rate as the semiconductor chip body.
6. A semiconductor package comprising:
a substrate;
a semiconductor chip attached to the substrate, the semiconductor chip including a semiconductor chip body having an arch-shaped groove in a backside thereof and a non-conductive material pattern filling the arch-shaped groove; and
a mold resin material encapsulating the semiconductor chip,
wherein a surface of the non-conductive material pattern is coplanar with a bottom surface of the semiconductor chip body.
7. The semiconductor package of claim 6 , wherein the semiconductor chip is electrically connected to the substrate through wires, the mold resin material encapsulating the semiconductor chip and wires.
8. The semiconductor package of claim 6 , wherein the non-conductive material pattern is a material having a solidity which is greater than that of the semiconductor chip body.
9. The semiconductor package of claim 6 , wherein the non-conductive material pattern has an adhesive property.
10. The semiconductor package of claim 6 , wherein the non-conductive material pattern includes an epoxy type polymer material or a silicon resin material.
11. The semiconductor package of claim 6 , wherein the non-conductive material pattern is attached to the substrate.