IP Library Granted Patent US 9,111,946
Granted Patent B2
US 9,111,946 · App. 13/722,340 · Granted Aug 18, 2015

Method of thinning a wafer to provide a raised peripheral edge

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Quick Facts
Patent No.
US 9,111,946
App. No.
13/722,340
Granted
Aug 18, 2015
Kind
B2
Abstract

A first area of a first surface of an encapsulated component can be thinned, the component including: a semiconductor chip having an active surface opposite the first surface, and an encapsulant extending outwardly from edges of the semiconductor chip. An entire area of the active surface may be aligned with the first area. After the abrading, a second area of the encapsulated component beyond the first area may have a thickness greater than a thickness of the first area. The second area can be configured to fully support the abraded encapsulated component in a state of the encapsulated component being manipulated by handling equipment.

Claims (21)

1. A method of thinning an encapsulated component, comprising:

abrading a first area of a first surface of an encapsulated component to reduce a thickness of the encapsulated component within the first area, the encapsulated component including:

an undiced semiconductor wafer comprising a plurality of semiconductor chips each being an integral portion of the wafer, the wafer having a semiconductor region extending continuously within the plurality of semiconductor chips and an active wafer surface defined by active surfaces of each of the semiconductor chips, the active wafer surface facing away from the first surface, the wafer having an edge bounding the active wafer surface, wherein the active wafer surface comprises a semiconductor device region and a peripheral portion extending from the edge of the wafer to the semiconductor device region,

a sacrificial structure overlying the semiconductor device region, and

an encapsulant contacting the peripheral portion of the active wafer surface and extending outwardly in first and second directions beyond the edge of the wafer,

wherein an entire area of the active wafer surface is aligned with the first area in the first and second directions,

the abrading being performed such that after the abrading, a second area of the encapsulated component beyond the first area has a thickness greater than the reduced thickness, wherein the second area is configured to fully support the abraded encapsulated component in a state in which the encapsulated component is manipulated by handling equipment.

2. The method of claim 1 , wherein the peripheral portion of the active wafer surface in contact with the encapsulant extends inwardly from the edge of the semiconductor wafer to a distance of at least 1.0 millimeters from the edge of the semiconductor wafer.

3. The method of claim 2 , wherein the peripheral portion of the active wafer surface in contact with the encapsulant extends from an edge of the sacrificial structure.

4. The method of claim 1 , wherein the reduced thickness of the encapsulated component is at least as great as a sum of the thickness of the semiconductor wafer after the abrading plus a thickness of the sacrificial structure overlying the semiconductor wafer.

5. The method of claim 1 , wherein the second area of the encapsulated component is a continuous area surrounding the first area in the first and second directions.

6. The method of claim 1 , wherein the second area of the encapsulated component is discontinuous within an area of the encapsulated component surrounding the first area in the first and second directions.

7. The method of claim 1 , wherein the encapsulated component further comprises a support component, the encapsulant mechanically coupling the support component with the semiconductor chip.

8. The method of claim 7 , wherein the support component is continuous and surrounds the first area in the first and second directions.

9. The method of claim 7 , wherein the support component is discontinuous within an area surrounding the first area in the first and second directions.

10. The method of claim 7 , wherein the support component comprises a solid metal.

11. The method of claim 1 , further comprising, prior to the abrading of the encapsulated component, forming the encapsulated component by forming the sacrificial structure overlying the active wafer surface and then depositing the encapsulant over at least one edge and over at least a portion of a non-active surface of the undiced semiconductor wafer opposite from the active wafer surface, the sacrificial structure protecting the active wafer surface from contact with the encapsulant.

12. The method of claim 11 , further comprising, after the abrading, removing at least a portion of the sacrificial structure.

13. The method of claim 1 , further comprising severing the semiconductor chips from the wafer after the abrading step.

14. The method of claim 1 , wherein the encapsulant extends beyond the active wafer surface in a direction away from the first surface such that the encapsulant within the first area has a thickness greater than the wafer after the abrading step.

15. The method of claim 1 , wherein the encapsulant abuts and extends from an edge of the sacrificial —structure.

Assignments (6)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0661 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073689/0793 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Jan 2, 2018
From: SCALARC, INC.
To: PACIFIC WESTERN BANK
Reel/Frame 044517/0526 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →