INTEGRATED AND NATURALIZED STATIC WEAR-LEVELING FOR BLOCK MAPPING
An embodiment is a technique to perform static wear leveling in a flash device. A first static block is popped from front of a first-in-first-out (FIFO) static pool when a static wear leveling condition is met. Data are copied from the first static block into an erased block to form a new block. The new block is pushed to end of the FIFO static pool. The static pool is part of a current static set and a next static set. Another embodiment is a technique to maintain a FIFO static pool. All valid data are consolidated when a data collection condition is met. An erased block is selected from a free set. All consolidated data are copied into the erased block to form a new block. The new block is pushed into the FIFO static pool.
1 . A method comprising:
popping a first static block from front of a first-in-first-out (FIFO) static pool when a static wear leveling condition is met;
copying data from the first static block into an erased block to form a new block; and
pushing the new block to end of the FIFO static pool,
wherein the static pool is part of a current static set and a next static set.
2 . The method of claim 1 further comprising:
erasing the first static block after copying the data.
3 . The method of claim 1 further comprising:
removing a second block in the FIFO static pool when the second block becomes invalid or mixed.
4 . A method comprising:
consolidating all valid data when a data collection condition is met;
selecting an erased block from a free set;
copying all consolidated data into the erased block to form a new block; and
pushing the new block to a first-in-first-out (FIFO) static pool,
wherein the static pool is part of a current static set and a next static set.
5 . The method of claim 4 wherein the instructions causing the processor to perform consolidating all valid data comprise instructions that cause the processor to perform operations comprising:
selecting quanta of valid data in at least a block where a majority of blocks in the at least a block contain invalid data; and
merging the quanta of valid data to fit within the erased block.
6 . The method of claim 4 wherein the free set contains erased blocks that are available for use.
7 . A circuit comprising:
a processor;
a memory coupled to the processor, the memory storing instructions that, when executed, cause the processor to perform operations comprising:
popping a first static block from front of a first-in-first-out (FIFO) static pool when a static wear leveling condition is met;
copying data from the first static block into an erased block to form a new block; and
pushing the new block to end of the FIFO static pool,
wherein the static pool is part of a current static set and a next static set.
8 . The circuit of claim 7 wherein the instructions further comprises instructions that cause the processor to perform operations comprising:
erasing the first static block after copying the data.
9 . The circuit of claim 7 wherein the instructions further comprises instructions that cause the processor to perform operations comprising:
removing a second block in the FIFO static pool when the second block becomes invalid or mixed.
10 . A circuit comprising:
a processor; and
a memory coupled to the processor, the memory storing instructions that, when executed, cause the processor to perform operations comprising:
consolidating all valid data when a data collection condition is met,
selecting an erased block from a free set,
copying all consolidated data into the erased block to form a new block, and
pushing the new block to a first-in-first-out (FIFO) static pool,
wherein the static pool is part of a current static set and a next static set.
11 . The circuit of claim 10 wherein the instructions causing the processor to perform consolidating all valid data comprises instructions that cause the processor to perform operations comprising:
selecting quanta of valid data in at least a block where a majority of blocks in the at least a block contain invalid data; and
merging the quanta of valid data to fit within the erased block.
12 . The circuit of claim 10 wherein the free set contains erased blocks that are available for use.