Physical layer loopback
In some embodiments, a chip comprises control circuitry to provide inband signals, inband output ports, and transmitters to transmit the inband signals to the inband output ports. The control circuitry selectively includes loopback initiating commands in the inband signals. Other embodiments are described and claimed.
1. An apparatus comprising:
a receiver to receive an in-band loopback request from a device over an interconnect comprising one or more serial point-to-point differential links, wherein each link of the one or more serial point-to-point differential links includes a plurality of lanes; and
a logic to:
interpret the in-band loopback request received from the receiver; and
enter a loopback state based at least in part on the loopback request,
wherein some but not all lanes of the plurality of lanes in the link enter loopback state based on the loopback request; and
adjust output voltage level and timing for a transmitter based at least in part on information in the loopback request, wherein the logic to adjust the output voltage level and timing until a miscompare is generated indicating a boundary of the voltage level and timing.
2. The apparatus of claim 1 , wherein the receiver is further configured to:
receive data over the interconnect; and
wherein the logic is further configured to:
loopback at least some of the received data while in the loopback state.
3. The apparatus of claim 2 , wherein the data is received from the device.
4. The apparatus of claim 2 , wherein the data is received over a particular lane of the interconnect and looping back includes sending a copy of the at least some of the received data to a transmitter on the particular lane.
5. The apparatus of claim 1 , wherein the logic is further configured to:
receive a signal;
interpret the signal to indicate an end of the loopback state; and
exit the loopback state based at least in part on the signal.
6. The apparatus of claim 5 , wherein the signal comprises an electrical idle exceeding a predetermined minimum time interval.
7. The apparatus of claim 5 , wherein the signal comprises at least one electrical idle ordered set.
8. The apparatus of claim 1 , wherein the in-band loopback request comprises a loopback initiating command.
9. The apparatus of claim 1 , wherein the in-band loopback request comprises data included in a Peripheral Component Interconnect Express (PCIe) training sequence.
10. The apparatus of claim 1 , wherein the in-band loopback request corresponds to a configuration event.
11. The apparatus of claim 1 , wherein the interconnect comprises at least one of a physical layer to support a Peripheral Component Interconnect Express (PCIe) protocol layer, a physical layer including one or more protocols.
12. The apparatus of claim 1 , wherein the interconnect comprises a Peripheral Component Interconnect Express compliant interconnect.
13. An apparatus comprising:
a control module to generate a loopback initiation request; and
a transmitter to send the loopback initiation request generated by the control module to a device as an in-band signal over an interconnect comprising one or more serial point-to-point differential links, wherein each link of the one or more serial point-to-point differential links includes a plurality of lanes,
wherein the loopback initiation request is to indicate that the device is to enter a loopback state,
wherein some but not all lanes of the plurality of lanes in the link enter the loopback state based on the loopback initiation request,
wherein a logic unit to adjust output voltage level and timing for the transmitter based at least in part on information in the loopback initiation request, and
wherein the logic unit to adjust the output voltage level and timing until a miscompare is generated indicating a boundary of the voltage level and timing.
14. The apparatus of claim 13 , wherein the transmitter to send data to the device, following the loopback initiation request; and wherein the apparatus further comprises a receiver to receive a copy of at least a portion of the data looped back by the device.
15. The apparatus of claim 13 , wherein the loopback initiation request comprises data to be included in a Peripheral Component Interconnect Express (PCIe) training sequence.
16. The apparatus of claim 15 , wherein the PCIe training sequence includes a loopback bit, wherein the loopback bit, when set, indicates that the device is to enter the loopback state.
17. The apparatus of claim 15 , wherein the PCIe training sequence comprises one or more ordered sets.
18. The apparatus of claim 15 , wherein the PCIe training sequence comprises a TS 1 training sequence.
19. The apparatus of claim 15 , wherein the PCIe training sequence comprises a TS 2 training sequence.
20. The apparatus of claim 13 , wherein the control module is further configured to: send a signal indicating an end to the loopback state.
21. The apparatus of claim 20 , wherein the signal comprises an electrical idle.
22. The apparatus of claim 20 , wherein the signal comprises at least on electrical idle ordered set.
23. The apparatus of claim 13 , wherein the interconnect comprises at least one of a physical layer to support a Peripheral Component Interconnect Express (PCIe) protocol layer, a physical layer including one or more protocols.
24. The apparatus of claim 13 , wherein the interconnect comprises a Peripheral Component Interconnect Express compliant interconnect.
25. An apparatus comprising:
a receiver to receive data over an interconnect including two or more ordered sets in a Peripheral Component Interconnect Express (PCIe) training sequence from a device over an interconnect comprising a point-to-point serial data link including a plurality of lanes, wherein each of the two or more ordered sets include a respective loopback bit set; and
a control module to:
enter a loopback state based at least in part on receiving the two or more ordered sets with loopback bits set from the receiver;
loopback at least some of the received data to the device during the loopback state, wherein some but not all lanes of the plurality of lanes in the point-to-point serial data link enter the loopback state based on the loopback bit set;
receive an electrical idle ordered set over the interconnect;
echo the electrical idle ordered set; and
exit the loopback state based at least in part on the electrical idle ordered set; and
adjust output voltage level and timing for a transmitter based at least in part on information in the loopback request, wherein the control module to adjust the output voltage level and timing until a miscompare is generated indicating a boundary of the voltage level and timing.
26. A system comprising:
a Peripheral Component Interconnect Express (PCIe)-compliant interconnect comprising one or more serial point-to-point differential links, wherein each link of the one or more serial point-to-point differential links includes a plurality of lanes;
a first device; and
a second device, wherein the second device is communicatively coupled to the first device using the PCIe-compliant interconnect and the second device includes:
a receiver to:
receive in-band loopback requests from the first device over the interconnect; and
cause the second device to enter a loopback state based at least in part on receiving a loopback request, wherein some but not all lanes of the plurality of lanes in the link enter the loopback state based on the loopback request; and
a transmitter to:
generate loopback requests; and
send loopback requests to the first device as in-band signals over the interconnect, wherein loopback requests from the second device is to indicate that the first device is to enter a loopback state,
wherein the receiver to adjust output voltage level and timing for the transmitter based at least in part on information in the loopback request, wherein the receiver to adjust the output voltage level and timing until a miscompare is generated indicating a boundary of the voltage level and timing.
27. The system of claim 26 , wherein the first device further comprises a receiver and a transmitter.
28. The system of claim 26 , wherein the first device comprises a first chip and the second device comprises a second chip.
29. The system of claim 26 , wherein the second device comprises a chip on a motherboard.
30. A method comprising:
receiving, by a receiver, an in-band loopback request from a device over an interconnect comprising one or more serial point-to-point differential links, wherein each of the one or more serial point-to-point differential links includes a plurality of lanes;
interpreting, by a control module, the in-band loopback request; and
entering, by the control module, a loopback state based at least in part on the loopback request, wherein some but not all lanes of the plurality of lanes in the link enter the loopback state based on the loopback request; and
adjusting output voltage level and timing for a transmitter based at least in part on information in the loopback request, wherein adjusting the output voltage level and timing is performed until a miscompare is generated indicating a boundary of the voltage level and timing.
31. The method of claim 30 , further comprising:
receiving data over the interconnect; and
looping back at least some of the received data while in the loopback state.
32. The method of claim 31 , wherein the data is received over a particular lane of the interconnect from a transmitting device and looping back includes sending a copy of the at least some of the received data to the transmitting device on the particular lane.
33. The method of claim 31 , further comprises:
receiving a signal by the control module;
interpreting, by the control module, the signal to indicate an end of the loopback state; and
exiting, by the control module, the loopback state based at least in part on the signal.
34. The method of claim 33 , wherein the signal comprises an electrical idle exceeding a predetermined minimum time interval.