Apparatus for ESD protection
A structure comprises an N+ region formed over a first fin of a substrate, a P+ region formed over a second fin of the substrate, wherein the P+ region and the N+ region form a diode, a shallow trench isolation region formed between the P+ region and the N+ region and a first epitaxial growth block region formed over the shallow trench isolation region and between the N+ region and the P+ region, wherein a forward bias current of the diode flows through a path underneath the shallow trench isolation region.
1. A structure comprising:
an N+ region formed over a first fin of a substrate;
a P+ region formed over a second fin of the substrate, wherein the P+ region and the N+ region form a diode;
a shallow trench isolation region formed between the P+ region and the N+ region; and
a first epitaxial growth block region formed over the shallow trench isolation region and between the N+ region and the P+ region, wherein a forward bias current of the diode flows through a path underneath the shallow trench isolation region, and wherein the P+ region and the N+ region are separated by the first epitaxial growth block region.
2. The structure of claim 1 , wherein:
the N+ region is formed in an n-well of the substrate; and
the P+ region is formed in the n-well of the substrate, and wherein the N+ region and the P+ region form a p-type electrostatic discharge (ESD) protection diode.
3. The structure of claim 1 , wherein:
the N+ region is formed in a p-well of the substrate; and
the P+ region is formed in the p-well of the substrate, and wherein the N+ region and the P+ region form an n-type ESD protection diode.
4. The structure of claim 1 , wherein:
the first epitaxial growth block region comprises silicon nitride.
5. The structure of claim 1 , wherein:
the first epitaxial growth block region is a dummy poly region.
6. The structure of claim 1 , further comprising:
a second epitaxial growth block region formed on an opposite side of the N+ region with respect to the first epitaxial growth block region; and
a third epitaxial growth block region formed on an opposite side of the P+ region with respect to the first epitaxial growth block region.
7. The structure of claim 1 , wherein:
the first fin and the second fin are separated by the shallow trench isolation region.
8. A structure comprising:
a first N+ region over a first fin in a p-well of a substrate;
a first P+ region over a second fin in the p-well of the substrate;
a first shallow trench isolation region formed between the first P+ region and the first N+ region; and
a first epitaxial growth block region formed over the first shallow trench isolation region and between the first N+ region and the first P+ region, and wherein the first P+ region and the first N+ region are separated by the first epitaxial growth block region.
9. The structure of claim 8 , further comprising:
a gate dielectric layer between the first epitaxial growth block region and the first shallow trench isolation region.
10. The structure of claim 8 , wherein:
the first fin and an adjacent fin are separated by an STI region.
11. The structure of claim 8 , wherein:
the second fin and an adjacent fin are separated by an STI region.
12. The structure of claim 8 , wherein:
the first N+ region and the first P+ region form a protection diode.
13. The structure of claim 12 , wherein:
the protection diode is an n-type diode.
14. The structure of claim 8 , wherein:
the first epitaxial growth block region is a dummy poly region.
15. The structure of claim 14 , wherein:
the dummy poly region comprises polycrystalline-silicon.