Methods and structure for carrier-less thin wafer handling

1. A method of forming a microelectronic assembly, comprising:

removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate, each of the integral supporting portions having a width and a first thickness extending along the entire width, wherein the first thickness is greater than a thickness of the thinned portions, at least some of the thinned portions each including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and

removing fully the integral supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, each individual thinned portion having a thickness less than the first thickness, at least some individual thinned portions including the interconnects.

2. The method of claim 1 , wherein the substrate consists essentially of semiconductor material and the removing material to form the processed substrate comprises removing some of the semiconductor material, the method further comprising forming a dielectric layer overlying the surface of the thinned portions prior to the step of removing the integral supporting portions.

3. The method of claim 1 , wherein the substrate consists essentially of a dielectric material which insulates the interconnects from one another, and the removing material to form the processed substrate comprises removing some of the dielectric material which insulates the interconnects.

4. The method of claim 1 , further comprising forming the substrate by steps including:

bonding confronting surfaces of first and second elements with one another and forming the interconnects extending through the first element, wherein the step of removing material of the substrate includes removing the material of the second element exposed at the portions of the surface to cause the electrically conductive interconnects to become exposed at the surface.

5. The method of claim 1 , wherein at least some of the thinned portions each include a plurality of active devices.

6. The method of claim 2 , further comprising:

forming an electrically conductive structure contacting at least some of the interconnects prior to the step of removing the supporting portions, wherein the electrically conductive structure is exposed at the surface.

7. The method of claim 1 , wherein during the step of removing material at the surface of the substrate, at least some of the thinned regions are formed so as to leave supporting portions surrounding the at least some thinned regions.

8. The method of claim 1 , wherein the step of removing the integral support portions further comprises:

sawing at least one first supporting portion of the substrate in a first direction and sawing at least one second supporting portion of the substrate in a second direction transverse to the first direction.

9. A method of forming a microelectronic assembly, comprising:

removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate, each of the integral supporting portions having a width and a first thickness extending along the entire width, wherein the first thickness is greater than a thickness of the thinned portions, at least some of the thinned portions each including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface;

removing fully the integral supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, each individual thinned portion having a thickness less than the first thickness, at least some individual thinned portions including the interconnects; and

forming an electrically conductive structure contacting at least some of the interconnects prior to the step of removing the integral supporting portions, wherein the electrically conductive structure is exposed at the surface.

10. The method of claim 9 , wherein the substrate consists essentially of semiconductor material and the removing material to form the processed substrate comprises removing some of the semiconductor material, the method further comprising forming a dielectric layer overlying the surface of the thinned portions prior to the step of removing the integral supporting portions.

11. The method of claim 9 , wherein the substrate consists essentially of a dielectric material which insulates the interconnects from one another, and the removing material to form the processed substrate comprises removing some of the dielectric material which insulates the interconnects.

12. The method of claim 9 , further comprising forming the substrate by steps including:

bonding confronting surfaces of first and second elements with one another and forming the interconnects extending through the first element, wherein the step of removing material of the substrate includes removing the material of the second element exposed at the portions of the surface to cause the electrically conductive interconnects to become exposed at the surface.

13. The method of claim 9 , wherein at least some of the thinned portions each include a plurality of active devices.

14. The method of claim 9 , wherein during the step of removing material at the surface of the substrate, at least some of the thinned regions are formed so as to leave supporting portions surrounding the at least some thinned regions.

15. The method of claim 9 , wherein the step of removing the integral support portions further comprises:

sawing at least one first supporting portion of the substrate in a first direction and sawing at least one second supporting portion of the substrate in a second direction transverse to the first direction.