Dynamic balancing of power across a plurality of processor domains according to power policy control bias
In an embodiment, a processor includes multiple domains including a core domain having at least one core to execute instructions and a graphics domain including at least one graphics engine to perform graphics operations and a power controller to control power consumption of the processor. The power controller may include a logic to receive an indication of a priority domain of the domains and to dynamically allocate power to the domains based on a power limit, one or more maximum domain frequency requests, and the priority domain indication. Other embodiments are described and claimed.
1. A processor comprising:
a plurality of domains including a core domain having at least one core to execute instructions;
a power cost table to store a plurality of entries, each entry associating a leakage power level, a first dynamic power level and a second dynamic power level with one of the plurality of domains for a given frequency of operation; and
a power controller to control power consumption of the processor, the power controller including a first logic to receive an indication of a priority domain of the plurality of domains and to dynamically allocate power to the plurality of domains based on a power limit, one or more maximum domain frequency requests, and the priority domain indication, wherein the first logic is to determine a power demand for a first operating level of the core domain based on a first number of cores at a peak demand level corresponding to the first dynamic power level, a second number of cores at an active demand level corresponding to the second dynamic power level, and a third number of cores at a leakage demand level corresponding to the leakage power level.
2. The processor of claim 1 , wherein the power controller is to first dynamically allocate a first portion of the power limit to the plurality of domains to enable each of the plurality of domains to operate at a minimum operating level.
3. The processor of claim 2 , wherein the power controller is to second dynamically allocate at least part of a remaining portion of the power limit to the priority domain.
4. The processor of claim 3 , wherein the power controller is to third dynamically allocate a remainder of the remaining portion of the power limit to at least another of the plurality of domains.
5. The processor of claim 3 , wherein the first logic is to perform a binary search bounded by minimum and maximum frequency values for the priority domain to determine a maximum operating level for the priority domain based on the at least part of the remaining portion of the power limit.
6. The processor of claim 5 , wherein the first logic is to further determine the maximum operating level based on a bias value to indicate a bias between the core domain and a graphics domain including at least one graphics engine to perform graphics operations.
7. The processor of claim 5 , wherein the power controller is to clip an operating request for the priority domain from a software agent to a minimum of the maximum operating level and the operating request.
8. The processor of claim 1 , wherein the first logic is to further determine the power demand based on an entry in the power cost table.
9. The processor of claim 1 , wherein the first logic is to perform the dynamic allocation based at least in part on the power demand.
10. The processor of claim 1 , further comprising a configuration storage to store the power limit, wherein the power limit is dynamically updatable by a software entity.
11. The processor of claim 10 , further comprising a second configuration storage to store the priority domain indicator, wherein the priority domain indicator is dynamically updateable by the software entity.
12. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
receiving a request to update a frequency of a first domain of a multi-domain processor;
calculating a minimum power demand for a plurality of domains of the multi-domain processor, including for a core domain, determining a first number of cores at a peak demand level, a second number of cores at an active demand level, and a third number of cores at a leakage demand level, and applying a corresponding level from an entry of a power allocation table to each of the first, second and third number of cores, the power allocation table to store a plurality of entries, each entry associating the leakage demand level, the peak demand level and the active demand level with one of the plurality of domains for a given frequency of operation, and allocating the minimum power demand to each of the plurality of domains;
determining if a portion of a power budget remains after the minimum power demand allocation; and
if so, allocating at least part of the remaining power budget to a priority of the plurality of domains.
13. The non-transitory machine-readable medium of claim 12 , wherein allocating the at least part of the remaining power budget comprises performing a binary search to determine a maximum operating frequency for the priority domain.
14. The non-transitory machine-readable medium of claim 13 , wherein the method further comprises allocating another part of the remaining power budget to at least another of the plurality of domains.
15. A system comprising:
A multi-domain processor having a plurality of domains including a core domain having at least one core to execute instructions, the multi-domain processor further including a power allocation table including a plurality of entries each to store, for a frequency and a voltage, a leakage power level, a first dynamic power level and a second dynamic power level, and a power allocation logic to receive a request to update a frequency of the core domain, calculate a minimum power demand for the plurality of domains and allocate a minimum power level to each of the plurality of domains, and allocate at least part of a remaining power budget to the core domain, wherein the power allocation logic is to determine a power demand for a first operating level of the core domain based on a first number of cores at a peak demand level corresponding to the first dynamic power level, a second number of cores at an active demand level corresponding to the second dynamic power level, and a third number of cores at a leakage demand level corresponding to the leakage power level; and
a dynamic random access memory (DRAM) coupled to the multi-domain processor.
16. The system of claim 15 , wherein the power allocation logic is to first dynamically allocate a first portion of the power budget to the plurality of domains to enable each of the plurality of domains to operate at a minimum performance level.
17. The system of claim 16 , wherein the power allocation logic is to second dynamically allocate the at least part of the remaining power budget to the core domain, and third dynamically allocate a remainder of the remaining power budget to a graphics domain including at least one graphics engine to perform graphics operations.
18. The system of claim 15 , wherein the multi-domain processor is to update the power allocation table when a temperature of the multi-domain processor changes by a threshold amount.