Normally off gallium nitride field effect transistors (FET)
View Patent ↗A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero-junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer. The power device further includes a floating gate located between the gate electrode and hetero-junction structure, wherein the gate electrode is insulated from the floating gate with an insulation layer and wherein the floating gate is disposed above and padded with a thin insulation layer from the hetero-junction structure and wherein the floating gate is charged for continuously applying a voltage to the 2DEG layer to pinch off the current flowing in the 2DEG layer between the source and drain electrodes whereby the HFET semiconductor power device is a normally off device.
1. A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprising:
a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer;
a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of said hetero-junction structure for controlling a current flow between said source and drain electrodes in said 2DEG layer;
said hetero-junction structure comprises said first and second semiconductor layers constituting a rectangular block with a longitudinal direction extending from the source electrode to the drain electrode; and
the gate electrode constituting a wrap-around gate wrapping around a segment of said rectangular block around sidewalls and a top surface of said middle segment of said rectangular block to control the 2DEG layer generated between the first and second semiconductor layers.
2. The HFET semiconductor power device of claim 1 wherein:
the first semiconductor layer is a gallium nitride (GaN) layer and the second semiconductor layer is an aluminum gallium nitride (AlGaN) layer disposed on top of the gallium nitride layer.
3. The HFET semiconductor power device of claim 1 further comprising:
a sapphire substrate for supporting the hetero-junction structure thereon.
4. The HFET semiconductor power device of claim 1 further comprising:
a floating gate located between said gate electrode and hetero-junction structure, wherein said gate electrode is insulated from said floating gate with an insulation layer and wherein said floating gate is disposed above and padded with a thin insulation layer from said hetero-junction structure and wherein the floating gate is negatively charged to shift a pinch off voltage of the 2DEG layer from a negative pinch off voltage to a positive pinch off voltage.
5. The HFET semiconductor power device of claim 1 wherein:
the first semiconductor layer is an N-type gallium nitride layer and the second semiconductor layer is an N-type AlGaN layer disposed on top of the gallium nitride layer.
6. The HFET semiconductor power device of claim 4 wherein:
the floating gate is negatively charged to shift a pinch off voltage of the 2DEG layer from a negative pinch off voltage to a positive pinch off voltage equal to or greater than three volts (3.0V).
7. The HFET semiconductor power device of claim 1 wherein:
the source electrode further includes an extended field plate extending from the source electrode and covering over the gate electrode.
8. The HFET semiconductor power device of claim 1 wherein:
the source electrode further includes an extended field plate extending from the source electrode and covering over the gate electrode wherein the field plate is insulated from the gate electrode with a thick insulation layer.