Mixed cell type battery module and uses thereof

1. A controller comprising logic to:

provide electric power from a first cell optimized to store electric energy with a relatively high density to a main processor circuit of a computing device when the computing device is operated in a lower power mode, the first cell comprising a first energy storage layer, a first anode conductor and a first cathode conductor; and

provide electric power from a second cell optimized to provide electric energy with a relatively high current level to the main processor circuit when the computing device is operated in a higher power mode, the second cell comprising a second energy storage layer, a second anode conductor and a second cathode conductor, the second energy storage layer to be thinner than the first energy storage layer, the second anode conductor to be thicker than the first anode conductor, and the second cathode conductor to be thicker than the second anode conductor.

2. The controller of claim 1 , the logic to:

monitor a voltage output of at least one of the first cell and the second cell; and

signal the main processor circuit of significant depletion of available electric power of at least one of the first cell and the second cell based on the voltage falling below a selected threshold.

3. The controller of claim 1 , the logic to:

monitor a first voltage output of the first cell;

monitor a second voltage output of the second cell; and

signal the main processor circuit of an inability to provide electric power to support the higher power mode based on the first voltage remaining above a first threshold and the second voltage falling below a second threshold.

4. The controller of claim 3 , the logic to:

detect provision of electric power sufficient to support the higher power mode by a power source; and

signal the main processor circuit of an ability to again provide electric power to support the higher power mode based on the provision of electric power by the power source.

5. The controller of claim 1 , the controller to:

receive a signal from the main processor indicative of an impending transition of the computing device to the higher power mode; and

provide electric power from the second cell to the main processor circuit based on receipt of the signal.

6. The controller of claim 1 , the first and second cells disposed in a casing of a battery module comprising a monitoring circuit disposed in the casing, the controller to employ the monitoring circuit to monitor one of a voltage of at least one of the first and second cells, a current flow of at least one of the first and second cells, and a temperature of at least one of the first and second cells.

7. The controller of claim 1 , the first and second cells based on a substantially similar battery chemistry, the battery chemistry comprising one of nickel cadmium (NiCd), nickel metal hydride (NiMH), lithium ion (Li-ion) and lithium polymer (Li-poly).

8. The controller of claim 1 , the first cell having a higher resistance and a higher capacitance than the second cell.

9. A device comprising:

a main processor circuit operable in either a lower power mode and a higher power mode, the higher power mode to consume a larger amount of electric energy than the lower power mode;

a controller to monitor a first voltage output of a first cell and a second voltage output of a second cell, the first cell comprising a first energy storage layer, a first anode conductor and a first cathode conductor, the second cell comprising a second energy storage layer, a second anode conductor and a second cathode conductor, the second energy storage layer to be thinner than the first energy storage layer, the second anode conductor to be thicker than the first anode conductor, and the second cathode conductor to be thicker than the second anode conductor; and

logic to:

receive a signal from the controller indicative of an inability to provide electric power to support the higher power mode based on the first voltage remaining above a first threshold and the second voltage falling below a second threshold; and

transition the main processor circuit from the higher power mode to the lower power mode based on receipt of the signal.

10. The device of claim 9 , comprising a clock circuit to provide a clock signal to the main processor circuit, the controller to cause the clock circuit to decrease a frequency of the clock signal to transition the main processor circuit from the higher power mode to the lower power mode based on receipt of the signal.

11. The device of claim 9 , comprising a display, the main processor to cause an indication of the inability to provide electric power to support the higher power mode to be visually presented on the display.

12. The device of claim 9 , the logic to receive a signal from the controller indicative of provision of electric power sufficient to support the higher power mode by a power source.

13. The device of claim 9 , the logic to receive a signal from the controller indicative of provision of electric power sufficient to support the higher power mode by the second cell.

14. The device of claim 9 , the logic to signal the controller with an indication of an impending transition of the computing device to the higher power mode to cause the controller to provide electric power from the second cell to the main processor circuit.

15. A computer-implemented method comprising:

providing electric power from a first cell optimized to store electric energy with a relatively high density to a main processor circuit of a computing device when the computing device is operated in a lower power mode, the first cell comprising a first energy storage layer, a first anode conductor and a first cathode conductor; and

providing electric power from a second cell optimized to provide electric energy with a relatively high current level to the main processor circuit when the computing device is operated in a higher power mode, the second cell comprising a second energy storage layer, a second anode conductor and a second cathode conductor, the second energy storage layer to be thinner than the first energy storage layer, the second anode conductor to be thicker than the first anode conductor, and the second cathode conductor to be thicker than the second anode conductor.

16. The computer-implemented method of claim 15 , comprising:

monitoring a voltage output of at least one of the first cell and the second cell; and

signaling the main processor circuit of significant depletion of available electric power of at least one of the first cell and the second cell based on the voltage falling below a selected threshold.

17. The computer-implemented method of claim 15 , comprising:

monitoring a first voltage output of the first cell;

monitoring a second voltage output of the second cell; and

signaling the main processor circuit of an inability to provide electric power to support the higher power mode based on the first voltage remaining above a first threshold and the second voltage falling below a second threshold.

18. The computer-implemented method of claim 17 , comprising:

detecting provision of electric power sufficient to support the higher power mode by a power source; and

signaling the main processor circuit of an ability to again provide electric power to support the higher power mode based on the provision of electric power by the power source.

19. The computer-implemented method of claim 15 , comprising:

receiving a signal from the main processor indicative of an impending transition of the computing device to the higher power mode; and

providing electric power from the second cell to the main processor circuit based on receipt of the signal.