Methods, systems and apparatus to reduce processor demands during encryption
Methods and apparatus are disclosed to reduce processor demands during encryption. A disclosed example method includes detecting a request for the processor to execute an encryption cipher determining whether the encryption cipher is associated with a byte reflection operation, preventing the byte reflection operation when a buffer associated with the encryption cipher will not cause a carryover condition, and incrementing the buffer via a shift operation before executing the encryption cipher.
1. A method to reduce a load on a processor, comprising:
detecting a request for the processor to execute an encryption cipher;
determining whether the encryption cipher is associated with a byte reflection operation;
preventing the byte reflection operation when a buffer associated with the encryption cipher will not cause a carryover condition; and
incrementing the buffer via a shift operation before executing the encryption cipher.
2. A method as defined in claim 1 , wherein the encryption cipher includes an Advanced Encryption Standard (AES) cipher.
3. A method as defined in claim 1 , wherein the byte reflection operation is based on a request for Internet Protocol Security (IPSec) communication.
4. A method as defined in claim 1 , wherein the buffer is associated with a Galois Counter Mode (GCM) block cipher mode.
5. A method as defined in claim 4 , further including determining a most significant bit associated with the buffer.
6. A method as defined in claim 5 , wherein the carryover condition is identified by comparing the most significant bit of the buffer with a maximum block size.
7. A method as defined in claim 1 , wherein preventing the byte reflection operation includes replacing a pshufb operation with a logical shift operation.
8. A method as defined in claim 1 , wherein the byte reflection operation includes a pshufb operation.
9. A method as defined in claim 1 , further including applying a pshufb operation to byte reflect the buffer when the carryover condition occurs.
10. A processor, comprising:
a cipher module interface to detect a request for the processor to execute an encryption cipher;
a byte order manager to determine whether the encryption cipher is associated with a byte reflection operation;
a buffer associated with the encryption cipher;
a carryover detector to prevent the byte reflection operation when the buffer will not exhibit a carryover condition; and
a counter manager to increment the buffer via a shift operation before the encryption cipher is executed.
11. A processor as defined in claim 10 , wherein the cipher module interface is to employ an Advanced Encryption Standard (AES) cipher.
12. A processor as defined in claim 10 , wherein the cipher module interface is to identify a request for Internet Protocol Security (IPSec) communication.
13. A processor as defined in claim 10 , wherein the buffer is associated with a Galois Counter Mode (GCM) block cipher mode.
14. A processor as defined in claim 13 , wherein the byte order manager is to determine a most significant bit associated with the buffer.
15. A processor as defined in claim 14 , wherein the carryover detector is to identify the carryover condition by comparing the most significant bit of the buffer with a maximum block size.
16. A processor as defined in claim 10 , wherein the counter manager is to replace a pshufb operation with a logical shift operation in response to preventing the byte reflection operation.
17. A processor as defined in claim 10 , wherein the byte reflection operation includes a pshufb operation.
18. A processor as defined in claim 10 , wherein the counter manager is to invoke a pshufb operation to byte reflect the buffer when the carryover condition occurs.
19. A tangible computer readable storage medium comprising instructions that, when executed, cause a processor to, at least:
in response to a request for the processor to execute an encryption cipher, determine whether the encryption cipher is associated with a byte reflection operation;
prevent the byte reflection operation when a buffer associated with the encryption cipher will not exhibit a carryover condition; and
increment the buffer via a shift operation before executing the encryption cipher.
20. A tangible computer readable storage medium as defined in claim 19 , wherein the instructions, when executed, cause the processor to initiate an Advanced Encryption Standard (AES) cipher.
21. A tangible computer readable storage medium as defined in claim 19 , wherein the instructions, when executed, cause the processor to initiate a Galois Counter Mode (GCM) block cipher mode.
22. A tangible computer readable storage medium as defined in claim 21 , wherein the instructions, when executed, cause the processor to determine a most significant bit associated with the buffer associated with the GCM block cipher mode.
23. A tangible computer readable storage medium as defined in claim 22 , wherein the instructions, when executed, cause the processor to identify the carryover condition by comparing the most significant bit of the buffer with a maximum block size.
24. A tangible computer readable storage medium as defined in claim 19 , wherein the instructions, when executed, cause the processor to replace a pshufb operation with a logical shift operation.
25. A tangible computer readable storage medium as defined in claim 19 , wherein the instructions, when executed, cause the processor to apply a pshufb operation to byte reflect the buffer when the carryover condition occurs.