Cache system and information-processing device
View Patent ↗According to one embodiment, a cache system includes a tag memory includes a volatile memory device, the tag memory includes ways and storing a tag for each line, a data memory includes a nonvolatile memory device including sense amplifiers for reading data, the data memory includes ways and storing data for each line, a comparison circuit configured to compare a tag included in an address supplied from an external with a tag read from the tag memory, and a controller configured to turn off a power of a sense amplifier for a way which is not accessed based on a comparison result of the comparison circuit.
1. A cache system comprising:
a tag memory comprising a volatile memory device, the tag memory comprising ways and storing a tag for each line;
a data memory comprising a nonvolatile memory device including sense amplifiers for reading data, the data memory comprising ways and storing data for each line;
a comparison circuit configured to compare a tag included in an address supplied from an external with a tag read from the tag memory; and
a controller configured to turn off a power of a sense amplifier for a way which is not accessed based on a comparison result of the comparison circuit.
2. The cache system of claim 1 , wherein
the data includes words,
the address includes a word address, and
the controller further turns off the power of a sense amplifier other than a sense amplifier corresponding to a word specified by the word address.
3. The cache system of claim 1 , wherein the data memory starts to read a line corresponding to the tag when receiving the tag included in the address.
4. The cache system of claim 1 , wherein each of the sense amplifiers comprises a switch configured to turn off the power.
5. The cache system of claim 1 , wherein
the data memory comprises a memory cell array having memory cells, word lines for selecting a row of the memory cell array, and bit lines for selecting a column of the memory cell array, and
the sense amplifiers are connected to the bit lines.
6. The cache system of claim 1 , wherein the data memory comprises an MRAM.
7. The cache system of claim 1 , wherein the tag memory comprises an SRAM.
8. A cache system comprising:
a tag memory comprising ways and storing a tag for each line;
a data memory comprising a nonvolatile memory device including sense amplifiers for reading data, the data memory comprising ways and storing data for each line;
a counter configured to hold a count indicating a elapsed time starting when a line is finally accessed for each line;
a comparison circuit configured to compare a tag included in an address supplied from an external with a tag read from the tag memory; and
a controller configured to determine the number of ways to be driven based on a count of a line specified by the tag included in the address, and to drive ways corresponding to the number of ways.
9. The cache system of claim 8 , wherein the controller increases the number of ways to be driven as the count becomes smaller.
10. The cache system of claim 8 , wherein the controller turns on a power of a sense amplifier for a way to be driven.
11. The cache system of claim 8 , wherein the data memory starts to read a line corresponding to the tag included in the address after a way is driven by the controller.
12. The cache system of claim 8 , further comprising an LRU (least recently used) memory storing LRU information indicating the order from the most recently accessed way for each line,
wherein the controller selects a way to be driven based on LRU information of a line specified by the address.
13. The cache system of claim 8 , wherein
the data includes words,
the address includes a word address, and
the controller turns on a power of a sense amplifier corresponding to a word specified by the word address among sense amplifiers for a way to be driven.
14. The cache system of claim 8 , wherein the controller turns off a power of a sense amplifier for a way which is not accessed based on a comparison result of the comparison circuit.
15. The cache system of claim 8 , wherein each of the sense amplifiers comprises a switch configured to turn off the power.
16. The cache system of claim 8 , wherein
the data memory comprises a memory cell array having memory cells, word lines for selecting a row of the memory cell array, and bit lines for selecting a column of the memory cell array, and
the sense amplifiers are connected to the bit lines.
17. The cache system of claim 8 , wherein the data memory comprises an MRAM.
18. The cache system of claim 8 , wherein the tag memory comprises an SRAM.
19. An information-processing device comprising:
a processor;
a cache system described in claim 1 ; and
a main memory.