Delay-locked-loop circuit
A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.
1. A delay-locked-loop (DLL) circuit, comprising:
a first DLL configured to adjust a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a first frequency; and
a second DLL configured to adjust the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a second frequency,
wherein the second DLL is configured to operate in response to a mode register set signal.
2. The DLL circuit as claimed in claim 1 , wherein the first frequency is a low frequency and the second frequency is a high frequency.
3. The DLL circuit as claimed in claim 1 , wherein the first DLL is configured to operate in response to the mode register set signal.
4. The DLL circuit as claimed in claim 1 , wherein the first DLL stores locking information of the first internal clock signal having a low frequency and the second DLL stores locking information of the second internal clock signal having a high frequency, and during a subsequent operation the DLL circuit generates an internal clock signal synchronized with the external clock signal using the locking information of the first internal clock signal and the locking information of the second internal clock signal.
5. The DLL circuit as claimed in claim 4 , wherein the locking information of the first internal clock signal is a delay amount of a delay line of the first DLL, and the locking information of the second internal clock signal is a delay amount of a delay line of the second DLL.
6. The DLL circuit as claimed in claim 1 , further comprising a selecting circuit configured to select one of the first internal clock signal and the second internal clock signal to generate an internal clock signal in response to the mode register set signal.
7. A delay-locked-loop (DLL) circuit, comprising:
a first DLL configured to adjust a delay time of a first external clock signal having a first frequency received from a first input terminal to generate a first internal clock signal synchronized with the first external clock signal; and
a second DLL configured to adjust a delay time of a second external clock signal having a second frequency received from a second input terminal to generate a second internal clock signal synchronized with the second external clock signal,
wherein the second DLL is configured to operate in response to a mode register set signal.
8. The DLL circuit as claimed in claim 7 , wherein the first frequency is a low frequency and the second frequency is a high frequency.
9. The DLL circuit as claimed in claim 7 , wherein the first DLL is configured to operate in response to the mode register set signal.
10. The DLL circuit as claimed in claim 7 , wherein the first DLL stores locking information of the first internal clock signal having a low frequency and the second DLL stores locking information of the second internal clock signal having a high frequency, and during a subsequent operation the DLL circuit generates an internal clock signal synchronized with the external clock signal using the locking information of the first internal clock signal and the locking information of the second internal clock signal.
11. A delay-locked-loop (DLL) circuit, comprising:
a first DLL configured to adjust a delay time of a first external clock signal having a low frequency received from a first input terminal to generate a first internal clock signal synchronized with the first external clock signal; and
a second DLL configured to adjust a delay time of a second external clock signal having a high frequency received from a second input terminal to generate a second internal clock signal synchronized with the second external clock signal.
12. The DLL circuit as claimed in claim 11 , wherein the first DLL stores locking information of the first internal clock signal having a low frequency and the second DLL stores locking information of the second internal clock signal having a high frequency, and in a subsequent operation the DLL circuit generates an internal clock signal synchronized with the external clock signal using the locking information of the first internal clock signal and the locking information of the second internal clock signal.
13. The DLL circuit as claimed in claim 11 , wherein the first DLL and the second DLL operate in response to a mode register set signal.
14. The DLL circuit as claimed in claim 11 , wherein the locking information of the first internal clock signal is a delay amount of a delay line of the first DLL, and the locking information of the second internal clock signal is a delay amount of a delay line of the second DLL.
15. The DLL circuit as claimed in claim 11 , further comprising a selecting circuit configured to select one of the first internal clock signal and the second internal clock signal to generate an internal clock signal in response to a mode register set signal.