Apparatus and method for memory-mapped register caching

1. A processor comprising:

an architectural register file implemented as a combination of a register file cache and an architectural register region within a level 1 (L1) data cache, wherein the architectural register file is further implemented to store data within a data memory area of the L1 data cache; and

a data location table (DLT) to store data indicating a location of each architectural register within the register file cache and/or the architectural register region within the L1 data cache,

wherein in response to detecting that data stored in the data memory area of the L1 data cache is needed for an instruction, data is transferred from the memory area of the L1 data cache to the register file cache and/or the architectural register region within the L1 data cache, and wherein the transfer to the register file cache is deferred until the data is actually needed for a computational instruction.

2. The processor as in claim 1 wherein the DLT comprises an entry for each architectural register of the architectural register file.

3. The processor as in claim 2 wherein the DLT comprises a first column containing pointers to the register file cache.

4. The processor as in claim 3 wherein the DLT comprises a second column containing pointers to the architectural register region within the L1 data cache.

5. The processor as in claim 1 further comprising:

a lower level cache (LLC) for storing data, wherein in response to detecting that the data needed for an instruction is not present in the register file cache and/or the architectural register region within the L1 data cache, data is transferred from the LLC to the register file cache and/or the architectural register region within the L1 data cache.

6. The processor as in claim 1 further comprising:

a tag cache to store L1 tag values, the tag cache to be queried to determine whether data needed for an instruction is stored within the L1 cache.

7. A method comprising:

implementing an architectural register file as a combination of a register file cache and an architectural register region within a level 1 (L1) data cache, and

storing data indicating a location of each architectural register within the register file cache and/or the architectural register region within the L1 data cache within a data location table (DLT) in response to detecting that data needed for an instruction is not present in the register file cache and/or the architectural register region within the L1 data cache, data being transferred from a lower level cache (LLC) to the register file cache and/or the architectural register region within the L1 data cache, wherein the transfer to the register file cache is deferred until the data is actually needed for a computational instruction.

8. The method as in claim 7 wherein the DLT comprises an entry for each architectural register of the architectural register file.

9. The method as in claim 8 wherein the DLT comprises a first column containing pointers to the register file cache.

10. The method as in claim 9 wherein the DLT comprises a second column containing pointers to the architectural register region within the L1 data cache.

11. The method as in claim 7 wherein the architectural register file is further implemented to store data within a data memory area of the L1 data cache.

12. The method as in claim 11 wherein, in response to detecting that data stored in the data memory area of the L1 data cache is needed for an instruction, data is transferred from the data memory area of the L1 data cache to the register file cache and/or the architectural register region within the L1 data cache.

13. The method as in claim 11 further comprising:

a tag cache to store L1 tag values, the tag cache to be queried to determine whether data needed for an instruction is stored within the L1 cache.