High performance light emitting diode with vias
View Patent ↗High performance light emitting diode with vias. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a plurality of filled vias configured to connect a doped region on one side of the light emitting diode to a plurality of contacts on the other side of the light emitting diode. The filled vias may comprise less that 10% of a surface area of the light emitting diode.
1. An article of manufacture comprising:
a light emitting diode comprising a plurality of filled vias configured to connect a doped region on one side of said diode to a plurality of contacts on the other side of said diode.
2. The article of manufacture of claim 1 wherein said vias comprise less than 10% of a surface area of said light emitting diode.
3. The article of manufacture of claim 1 wherein a distance between any two vias in less than 200 μm.
4. The article of manufacture of claim 1 further comprising a transparent conductor on said one side of said diode, and wherein said plurality of filled vias are electrically coupled to said transparent conductor.
5. The article of manufacture of claim 1 further comprising a plurality of conductive traces on said one side of said diode, and wherein said plurality of filled vias are electrically coupled to said conductive traces.
6. The article of manufacture of claim 1 further comprising:
a phosphor layer and an optical element bonded to said one side of said diode.
7. The article of manufacture of claim 1 further comprising:
a carrier wafer bonded to said plurality of filled vias.
8. The article of manufacture of claim 7 wherein said carrier wafer comprises at least one material of the set of silicon, ceramic, glass, tungsten, molybdenum, invar, aluminum, nickel, steel, brass and copper.
9. The article of manufacture of claim 7 wherein said carrier wafer comprises a printed circuit board laminate.
10. The article of manufacture of claim 7 wherein said carrier wafer is characterized as having a thermal conductivity greater than 10 W/mK.
11. The article of manufacture of claim 7 wherein said carrier wafer is further coupled to a heat sink device.
12. The article of manufacture of claim 5 wherein said conductive traces are placed laterally on top of the surface of said carrier wafer and are configured to make electrical contact with external circuitry.
13. The article of manufacture of claim 5 wherein said conductive traces are placed laterally on top of the surface of said carrier wafer and are configured to make electrical contact with external circuitry, while a second electrode is configured to make electrical contact with external circuitry through the thickness of said carrier wafer.
14. The article of manufacture of claim 7 wherein both electrodes or said light emitting diode connect to external circuitry through the thickness of said carrier wafer.
15. The article of manufacture of claim 1 wherein a substrate utilized for growing said light emitting diode is absent.
16. The article of manufacture of claim 1 further comprising
electronics to convert a source of alternating current to direct current for use by said light emitting diode; and
a base to couple said electronics to said source of alternating current.
17. A light emitting diode apparatus comprising:
an n-doped semiconductor region;
a multiple quantum well (MQW) region disposed on said n-doped semiconductor region;
a p-doped semiconductor region disposed on said MQW region;
a plurality of filled vias through said p-doped semiconductor region and through said MQW region, contacting said n-doped semiconductor region, and
wherein both terminals of said light emitting diode apparatus are on the same side of said light emitting diode apparatus as said p-doped semiconductor region.
18. The light emitting diode apparatus of claim 17 wherein a surface of said n-doped semiconductor region away from said MQW region is free of electrical contacts.
19. An apparatus comprising:
a light emitting diode comprising:
an n-doped semiconductor region;
a multiple quantum well (MQW) region disposed on said n-doped semiconductor region;
a p-doped semiconductor region disposed on said MQW region;
a plurality of filled vias through said p-doped semiconductor region and through said MQW region, contacting said n-doped semiconductor region;
a carrier substrate;
a conductive pattern supported by said carrier substrate; and
metal for electrically coupling said plurality of filled vias to said conductive pattern.
20. The apparatus of claim 19 wherein said carrier substrate is configured to couple thermal energy away from said light emitting diode.