MOS-gated power devices, methods, and integrated circuits
View Patent ↗MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances.
1. A substantially vertical device comprising:
a first-conductivity-type source region;
an insulated trench having an approximately vertical sidewall;
a gate electrode;
a semiconductor body region positioned so that voltage bias applied to the gate electrode can induce inversion in said body region to thereby create a lateral channel; said body region being positioned to separate said source region from said trench;
a first-conductivity type drain extension region positioned in proximity to said trench, and leading from said channel to said sidewall of said trench;
permanent electrostatic charge positioned near said sidewall in density sufficient to invert at least some second-conductivity semiconductor material adjacent thereto; and
a conductive shield layer which is positioned above said insulated trench, and not electrically connected to said gate.
2. The device of claim 1 , wherein said insulated trench, below said shield, is completely filled with dielectric.
3. The device of claim 1 , wherein said shield is taller in height than said gate electrode.
4. The device of claim 1 , wherein said shield lies partly within said trench.
5. The device of claim 1 , wherein said shield lies entirely within said trench.
6. The device of claim 1 , wherein said shield is wider than said trench.
7. The device of claim 1 , further comprising a lightly doped region, of opposite conductivity type to said body, which is interposed between said trench and the location of said channel.
8. The device of claim 1 , wherein said trench penetrates from the surface of a semiconductor mass into a p-type layer, and also penetrates therethrough into an n-type drain layer.
9. The device of claim 1 , wherein said gate electrode and said shield are both made of silicide.
10. The device of claim 1 , wherein said permanent electrostatic charge comprises embedded cesium ions.
11. The device of claim 1 , built in a semiconductor structure which includes an epitaxial layer over an N+ buried layer over a P+ substrate, wherein said buried layer is contacted by a sinker diffusion.
12. A substantially vertical semiconductor device comprising:
an insulated trench;
a surface insulation layer containing at least two physically separated gate electrode portions;
a body region positioned so that a voltage bias applied to one of the gate electrodes will cause an inversion layer in said body region;
permanent charges positioned in said insulation material; and
a conductive shield layer positioned between said gate electrodes within said surface insulation layer.
13. The device of claim 12 , wherein said insulated trench, below said shield, is completely filled with dielectric.
14. The device of claim 12 , wherein said shield is taller in height than said gate electrodes.
15. The device of claim 12 , wherein said shield lies partly within said trench.
16. The device of claim 12 , wherein said shield lies entirely within said trench.
17. The device of claim 12 , wherein said shield is wider than said trench.
18. The device of claim 12 , further comprising a lightly doped region, of opposite conductivity type to said body, which is interposed between said trench and the location of said channel.
19. The device of claim 12 , wherein said trench penetrates from the surface of a semiconductor mass into a p-type layer, and also penetrates therethrough into an n-type drain layer.
20. The vertical semiconductor device of claim 12 , further comprising a drain region wherein said conductive shield electrode reduces gate-drain capacitance.