Multi-chip package assembly with improved bond wire separation
View Patent ↗A multi-chip package is disclosed that has a construction capable of preventing and/or reducing electrical shorts caused by shifts in bond wires. The multi-chip package includes a die attach formed between connection points of a bond wire. The die attach is made of a non-conductive material and can be constructed so as to support or encompass a portion of the bond wire. By contacting the bond wire, the die attach restricts the motion of the bond wire by acting as a physical barrier to the bond wire's movement and/or as a source of friction. In this manner, undesired position shifts of the bond wires can be prevented, reducing device failures and allowing for improved manufacturing allowances.
1. A multi-chip package, comprising:
a first semiconductor die having a first metal contact;
a second semiconductor die that overlaps the first semiconductor die, the second semiconductor die having a second metal contact;
a plurality of lead fingers;
a first bond wire electrically connecting a first one of the plurality of lead fingers to the first metal contact of the first semiconductor die;
a second bond wire electrically connecting a second one of the plurality of lead fingers to the second metal contact of the second semiconductor die;
a first die attach composed of an insulating material, disposed on a surface of the first semiconductor, and between the first metal contact and the first one of the plurality of lead fingers, the first die attach restricting relative motion of the first bond wire; and
a second die attach having at least one of a different size and a different shape from the first die attach and disposed on a surface of the second semiconductor die.
2. The multi-chip package of claim 1 , wherein the second die attach is composed of an insulating material and is disposed between the second metal contact and the second one of the plurality of lead fingers, the second die attach restricting relative motion of the second bond wire.
3. The multi-chip package of claim 1 , wherein the first bond wire is disposed so as to contact a top surface of the first die attach.
4. The multi-chip package of claim 1 , wherein the first bond wire is disposed so as to pass through the first die attach.
5. The multi-chip package of claim 4 , wherein the second bond wire is disposed so as to contact a top surface of the first die attach.
6. The multi-chip package of claim 1 , wherein the first die attach is disposed along a plurality of edges of the first semiconductor die.
7. The multi-chip package of claim 6 , wherein a first portion of the first die attach formed along a first edge of the plurality of edges of the first semiconductor die is separated discontinuous with a second portion of the first die attach formed along a second edge of the plurality of edges of the first semiconductor die.
8. The multi-chip package of claim 6 , wherein the first die attach is continuous between the plurality of edges.
9. The multi-chip package of claim 1 , wherein the second die attach is configured to restrict relative movement of the second bond wire.
10. The multi-chip package of claim 9 , wherein the second die attach has a different cross-sectional shape than the first die attach.
11. The multi-chip package of claim 9 , wherein the second bond wire passes through the second die attach, and wherein the second bond wire contacts the upper surface of the first die attach.
12. A multi-chip package, comprising:
a first semiconductor die having a metal contact;
a second semiconductor die that overlaps the first semiconductor die;
a lead finger;
a bond wire electrically connecting the metal contact and the lead finger;
a non-conductive die attach disposed between the metal contact and the lead finger and restricting relative movement of the bond wire, the non-conductive die attach being disposed on a surface of the first semiconductor die; and
a second die attach having a different cross-sectional shape than the non-conductive die attach, the second die attach being disposed on a surface of the second semiconductor die.
13. The multi-chip package of claim 12 , wherein the second die attach is configured to restrict relative movement of the bond wire.
14. The multi-chip package of claim 1 , wherein the second die attach extends continuously between a plurality of edges of the second semiconductor die.
15. The multi-chip package of claim 1 , wherein the second semiconductor die only partially overlaps the first semiconductor die, such that the first metal contact is exposed.