Host controlled enablement of automatic background operations in a memory device
A host that is coupled to a memory device is configured to read a status register of the memory device to determine if the memory device supports host controlled enablement of automatic background operations. The memory device responds to the host regarding whether the memory device supports host controlled enablement of automatic background operations. The host can enable the automatic background operations if the memory device supports this feature. The host can then set a time period in the memory device that is indicative of when the memory device can automatically perform the background operations.
1. A method for host controlled enablement of an automatic background operation in a memory device, the method comprising:
determining at the host whether the memory device indicates that the memory device supports host controlled enablement of the automatic background operation; and
using the host to configure the memory device to perform the automatic background operation in the memory device in response, at least in part, to determining at the host that the memory device indicates that the memory device supports the host controlled enablement of the automatic background operation.
2. The method of claim 1 and further comprising writing a time period value to a register of the memory device.
3. The method of claim 2 wherein the time period is a time that the memory device should wait before automatically performing the background operation.
4. The method of claim 2 wherein the time period is a time that the memory device should wait before enabling the automatic background operation.
5. The method of claim 1 and further comprising transmitting a start command to the memory device configured to indicate to the memory device to start the automatic background operation.
6. The method of claim 1 wherein determining at the host whether the memory device supports host controlled enablement of the automatic background operation comprises the host reading a register of the memory device.
7. The method of claim 1 wherein using the host to configure the memory device to perform the automatic background operation comprises the host transmitting control data to the memory device.
8. The method of claim 1 wherein using the host to configure the memory device to perform the automatic background operation comprises the host writing control data to a register of the memory device.
9. A method for host controlled enablement of an automatic background operation in a memory device, the method comprising:
determining if the memory device supports host controlled enablement of the automatic background operation;
enabling the automatic background operation in the memory device based, at least in part, on determining that the memory device supports host controlled enablement of the automatic background operation;
the host writing a time period value to a first register of the memory device; and
the host writing a unit of measure value for the time period value to a second register of the memory device.
10. The method of claim 9 wherein the host writing comprises the host directly writing to the first register without intervention of a controller of the memory device.
11. The method of claim 9 wherein the host writing comprises the host writing to the first register with intervention of a controller of the memory device.
12. A method for host controlled enablement of an automatic background operation in a memory device, the method comprising:
determining if the memory device supports host controlled enablement of the automatic background operation;
enabling the automatic background operation in the memory device based, at least in part, on determining that the memory device supports host controlled enablement of the automatic background operation;
wherein determining if the memory device supports host controlled enablement of the automatic background operation comprises the host reading a register of the memory device; and
wherein the host reading a first state from the register indicates that the memory device supports host controlled enablement of the automatic background operation and the host reading a second state from the register indicates that the memory device does not support host controlled enablement of the automatic background operation.
13. A system comprising:
a host; and
a memory device coupled to the host;
wherein the host is configured to determine whether the memory device indicates that the memory device supports host controlled enablement of an automatic background operation; and
wherein the host is configured to configure the memory device to perform the automatic background operation in the memory device in response, at least in part, to the host determining that the memory device indicates that the memory device supports the host controlled enablement of the automatic background operation.
14. The system of claim 13 wherein the memory device further comprises a plurality of registers comprising a status register, an enablement register, and a time register.
15. The system of claim 14 wherein the plurality of registers further comprises a unit of measure register associated with the time register.
16. The system of claim 14 wherein the status register is a read only register and the enablement register and time register are write/read registers.
17. The system of claim 14 wherein the status register is not programmable by the host.
18. The system of claim 14 wherein the host is configured to write control data to the enablement register wherein the control data is configured to enable or disable automatic performance of the automatic background operation by the memory device.
19. The system of claim 14 wherein the host is configured to write a time period value to the time register wherein the time period value is indicative of when the memory device can automatically perform the automatic background operation.
20. The system of claim 14 wherein the host is configured to write a time period value to the time register wherein the time period value is indicative of a time when the memory device is enabled for the automatic background operation.
21. The system of claim 13 and further comprising a register having different register bits configured to selectively enable different automatic background operations.