Graphene layer transfer
A method to transfer a layer of graphene from one substrate to another substrate is provided. The method includes providing a first layered structure including, from bottom to top, a copper foil, a layer of graphene, an adhesive layer and a carrier substrate. The copper foil is removed exposing a surface of the layer of graphene. Next, an oxide bonding enhancement dielectric layer is formed on the exposed surface of the layer of graphene. A second layered structure including a receiver substrate and a dielectric oxide layer is provided. Next, an exposed surface of the dielectric oxide layer is bonded to an exposed surface of the oxide bonding enhancement dielectric layer. The carrier substrate and the adhesive layer are removed exposing the layer of graphene.
1. A semiconductor structure comprising, from bottom to top,
a receiver substrate;
a dielectric oxide layer located directly on an entirety of an uppermost surface of said receiver substrate;
an oxide bonding enhancement dielectric layer located directly on an entirety of an uppermost surface of said dielectric oxide layer, wherein said oxide bonding enhancement dielectric layer comprises a silsesquioxane; and
a layer of graphene located directly on an entirety of an uppermost surface of said oxide bonding enhancement dielectric layer, wherein said oxide bonding enhancement dielectric layer has outermost sidewall edges that are vertically coincident to outer sidewall edges of said oxide dielectric layer.
2. The semiconductor structure of claim 1 , wherein said oxide bonding enhancement dielectric layer comprises hydrogen silsesquioxane, or methyl silsesquioxane.
3. The semiconductor structure of claim 1 , wherein said receiver substrate comprises a semiconductor material.
4. The semiconductor structure of claim 1 , wherein said layer of graphene comprises a monolayer.
5. A semiconductor structure comprising:
a receiver substrate;
a dielectric oxide layer located directly on an entirety of an uppermost surface of said receiver substrate;
an oxide bonding enhancement dielectric layer located directly on an entirety of an uppermost surface of said dielectric oxide layer, wherein said oxide bonding enhancement dielectric layer comprises a silsesquioxane; and
graphene-containing device located atop the oxide bonding enhancement dielectric layer, wherein said graphene-containing device includes at least a layer of graphene that serves as a channel of a field effect transistor and has a bottommost surface in direct contact with an entirety of an uppermost surface of the oxide bonding enhancement dielectric layer, and wherein said oxide bonding enhancement dielectric layer has outermost sidewall edges that are vertically coincident to outer sidewall edges of said oxide dielectric layer and an oxide to oxide bonding interface is present between said dielectric oxide layer and said oxide bonding enhancement dielectric layer.
6. The semiconductor structure of claim 5 , wherein said dielectric oxide layer is comprised of a different dielectric material than the oxide bonding enhancement dielectric layer.
7. The semiconductor structure of claim 5 , wherein said oxide bonding enhancement dielectric layer comprises hydrogen silsesquioxane, or methyl silsesquioxane.
8. The semiconductor structure of claim 5 , wherein said receiver substrate comprises a semiconductor material.
9. The semiconductor structure of claim 5 , wherein said silsesquioxane is a cross-linked dielectric material.
10. The semiconductor structure of claim 5 , wherein said silsesquioxane is a cross-linked dielectric material.
11. A semiconductor structure comprising:
a receiver substrate;
a dielectric oxide layer located directly on an entirety of an uppermost surface of said receiver substrate;
an oxide bonding enhancement dielectric layer located directly on an entirety of an uppermost surface of said dielectric oxide, wherein said oxide bonding enhancement dielectric layer comprises a silsesquioxane; and
a graphene-containing device located atop the oxide bonding enhancement dielectric layer, wherein said graphene-containing device includes at least a layer of graphene having a bottommost surface in direct contact with an uppermost surface of the oxide bonding enhancement dielectric layer, and wherein said oxide bonding enhancement dielectric layer has outermost sidewall edges that are vertically coincident to outer sidewall edges of said oxide dielectric layer.
12. The semiconductor structure of claim 11 , wherein said layer of graphene serves as a channel of a field effect transistor.
13. The semiconductor of claim 12 , wherein said field effect transistor comprises a gate dielectric layer in direct contact with an exposed surface of the layer of graphene, a gate conductor overlying a portion of the gate dielectric layer, a source contact and a drain contact, said source and drain contacts each having a bottommost surface in direct contact with an uppermost surface of the layer of graphene.
14. The semiconductor structure of claim 13 , wherein said gate dielectric layer is present on exposed sidewalls and atop each of the source contact and the drain contact.
15. The semiconductor structure of claim 13 , wherein said source contact and said drain contact each comprise a conductive material.