Variable-precision distributed arithmetic multi-input multi-output equalizer for power-and-area-efficient optical dual-polarization quadrature phase-shift-keying system
A variable-precision distributed arithmetic (VPDA) multi-input multi-output (MIMO) equalizer is presented to reduce the size and dynamic power of 112 Gbps dual-polarization quadrature phase-shift-keying (DP-QPSK) coherent optical communication receivers. The VPDA MIMO equalizer compensates for channel dispersion as well as various non-idealities of a time-interleaved successive approximation register (SAR) based analog-to-digital converter (ADC) simultaneously by using a least mean square (LMS) algorithm. As a result, area-hungry analog domain calibration circuits are not required. In addition, the VPDA MIMO equalizer achieves 45% dynamic power reduction over conventional finite impulse response (FIR) equalizers by utilizing the minimum required resolution for the equalization of each dispersed symbol.
1. A variable-precision distributed arithmetic (VPDA) multi-input multi-output (MIMO) equalizer connected to outputs of a plurality of analog-to-digital converters (ADCs) based on time-interleaved successive approximation registers, the VPDA MIMO equalizer comprising:
a plurality of sub-equalizers classified into a first sub-equalizers group and a second sub-equalizers group, wherein each of a plurality of sub-equalizers included in the first sub-equalizers group is connected to outputs of a first ADC group and each of a plurality of sub-equalizers included in the second sub-equalizers group is connected to outputs of a second ADC group; and
a decision unit configured to determine recovered data using an output symbol of the plurality of sub-equalizers,
wherein one sub-equalizer included in the first sub-equalizers group relates to other one sub-equalizer included in the second sub-equalizers group, and the recovered data is determined by the decision unit based on outputs of the one sub-equalizer and the other one sub-equalizer,
wherein each of the plurality of sub-equalizers comprises a plurality of additional-equalizers for distributed arithmetic, and each of the additional-equalizers corresponds to one of bits according to a resolution of the ADCs.
2. The VPDA MIMO equalizer of claim 1 , wherein one additional-equalizer of the one sub-equalizer relates to other one additional-equalizer of the other one sub-equalizer, and the one output symbol is determined by the decision unit based on an output of the one additional-equalizer and an output of the other one additional-equalizer.
3. The VPDA MIMO equalizer of claim 1 , wherein outputs of the ADCs corresponding to i-th bit of the bits is inputted to i-th additional-equalizers of the plurality of sub-equalizers.
4. The VPDA MIMO equalizer of claim 1 , wherein each of the plurality of additional-equalizers comprises a plurality of finite impulse responses (FIR) filters.
5. The VPDA MIMO equalizer of claim 4 , wherein one part of the plurality of FIR filters is connected to outputs of one ADC of the first ADC group (or the second ADC group), and another part of the plurality of FIR filters is connected to outputs of other one ADC of the first ADC group (or the second ADC group).
6. The VPDA MIMO equalizer of claim 1 , wherein the plurality of additional-equalizers is configured to repeatedly compute an equalized symbol for a resolution sequentially increasing by a determination of a range checker according to a sequence from the most significant bit (MSB) of the bits towards the least significant bit (LSB) of the bits.
7. The VPDA MIMO equalizer of claim 6 , further comprising:
the range checker is configured to determine whether a higher resolution than a present is required based on a value of the equalized symbol of the present resolution.
8. The VPDA MIMO equalizer of claim 1 , wherein coefficients with each of bits according to a resolution of the ADCs are combined with filter coefficients of FIR filters by at least one of a distributed arithmetic (DA) scheme and a least mean square (LMS) algorithm.
9. The VPDA MIMO equalizer of claim 8 , wherein each of outputs of the ADCs is multiplied with the combined coefficients and each of outputs of the FIR filters is combined.
10. A variable-precision (VP) equalizer comprising:
a plurality of additional-equalizers, configured to repeatedly compute an equalized symbol for a resolution sequentially increasing by a determination of a range checker according to a sequence from the most significant bit (MSB) towards the least significant bit (LSB) of bits of a digital value;
a decision unit configured to determine recovered data using the equalized symbol of the plurality of additional-equalizers; and
the range checker configured to determine whether a higher resolution than a present resolution is required based on a value of the equalized symbol for the present resolution.
11. The VP equalizer of claim 10 , wherein the digital value is a coefficient for the equalization and i-th resolution bits of the digital value are connected to i-th additional-equalizers.
12. The VP equalizer of claim 10 , wherein the digital value is an output of an analog-to-digital converter (ADC) and i-th resolution bits of outputs of the ADC are inputted to i-th additional-equalizers.
13. A receiver comprising:
an analog-to-digital converter (ADC); and
a variable-precision (VP) equalizer connected to an output of the ADC, the VP equalizer comprising:
a plurality of additional-equalizers configured to repeatedly compute an equalizer symbol for a resolution sequentially increasing by a determination of a range checker according to a sequence from the most significant bit (MSB) towards the least significant bit (LSB) of bits of a digital value;
a decision unit configured to determine recovered data using the equalized symbol of the plurality of additional-equalizers; and
the range checker configured to determine whether a higher resolution than a present resolution is required based on a value of the equalized symbol for the present resolution.
14. The receiver of claim 13 , wherein the digital value is a coefficient for the equalization and i-th resolution bits of the digital value are connected to i-th additional-equalizers.
15. The receiver of claim 13 , wherein the digital value is an output of the ADC and i-th resolution bits of outputs of the ADC are inputted to i-th additional-equalizers.
16. A distributed-arithmetic (DA) equalizer comprising:
a plurality of additional-equalizers, each of the additional-equalizers being connected to different coefficients corresponding to one of bits according to a resolution of an analog-to-digital converter (ADC) based on successive approximation registers (SAR), wherein each of the additional-equalizers is configured to compute an equalized symbol for the resolution according to a sequence, wherein the resolution is sequentially increasing by a determination of range checker, and wherein the sequence is from the most significant bit (MSB) towards the least significant bit (LSB) of the bits of the SAR ADC;
a decision unit configured to determine recovered data using a sum of the equalized symbols of the plurality of additional-equalizers; and
the range checker configured to determine whether a higher resolution than a present resolution is required based on a value of the equalized symbol for the present resolution.