Apparatus with a memory controller configured to control access to randomly accessible non-volatile memory
View Patent ↗An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.
1. An apparatus comprising:
a printed circuit board (PCB) having a plurality of printed circuit board traces;
a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces;
a plurality of randomly accessible non-volatile memory integrated circuits coupled to the printed circuit board, wherein the memory controller to control in parallel at least two of the plurality of randomly accessible non-volatile memory integrated circuits; and
a plurality of support integrated circuits coupled between the memory controller and the plurality of randomly accessible non-volatile memory integrated circuits, wherein each of the plurality of support integrated circuits to buffer addresses and data, and multiplex and de-multiplex data to and from the plurality of randomly accessible non-volatile memory integrated circuits.
2. The apparatus of claim 1 , wherein
the plurality of support integrated circuits each include
a many-to-one bus multiplexer to write data onto a data bus on the printed circuit board, and
a one-to-many bus demultiplexer to read data from the data bus into one or more of the randomly accessible non-volatile memory integrated circuits.
3. The apparatus of claim 1 , wherein
the plurality of randomly accessible non-volatile memory integrated circuits are mounted to the printed circuit board and coupled to one or more of the printed circuit board traces, and
the plurality of support integrated circuits are mounted to the printed circuit board and coupled to one or more of the printed circuit board traces.
4. The apparatus of claim 1 , wherein
the plurality of randomly accessible non-volatile memory integrated circuits and the plurality of support integrated circuits are mounted to a plurality of non-volatile memory modules, and
the printed circuit board further includes a plurality of sockets into which the plurality of non-volatile memory modules are plugged.
5. The apparatus of claim 1 , wherein
the printed circuit board further has an edge connector to plug into an expansion socket on a mother-board, and
the memory controller is further coupled to the edge connector.
6. The apparatus of claim 1 wherein
the plurality of randomly accessible non-volatile memory integrated circuits are NOR flash electrically erasable programmable read only memory (EEPROM) integrated circuits.
7. An apparatus comprising:
a printed circuit board (PCB) having a plurality of printed circuit board traces;
a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces;
a plurality of randomly accessible non-volatile memory integrated circuits coupled to the printed circuit board, wherein the memory controller to control in parallel at least two of the plurality of randomly accessible non-volatile memory integrated circuits; and
a plurality of support integrated circuits coupled between the memory controller and the plurality of randomly accessible non-volatile memory integrated circuits, wherein the plurality of support integrated circuits to buffer addresses and data, and multiplex and de-multiplex data to and from the plurality of randomly accessible non-volatile memory integrated circuits, wherein each of the plurality of support integrated circuits includes
a cross bar switch coupled between the memory integrated circuits and a data bus coupled to the memory controller, the switch to write data onto the data bus from the memory integrated circuits, the switch to further read data from the data bus and couple the data into one or more of the memory integrated circuits.
8. The apparatus of claim 7 , wherein
the plurality of randomly accessible non-volatile memory integrated circuits are mounted to the printed circuit board and coupled to one or more of the printed circuit board traces, and
the plurality of support integrated circuits are mounted to the printed circuit board and coupled to one or more of the printed circuit board traces.
9. The apparatus of claim 7 , wherein
the plurality of randomly accessible non-volatile memory integrated circuits and the plurality of support integrated circuits are mounted to a plurality of non-volatile memory modules, and
the printed circuit board further includes a plurality of sockets into which the plurality of non-volatile memory modules are plugged.
10. The apparatus of claim 7 , wherein
the printed circuit board further has an edge connector to plug into an expansion socket on a mother-board, and
the memory controller is further coupled to the edge connector.
11. The apparatus of claim 7 , wherein
the plurality of randomly accessible non-volatile memory integrated circuits are NOR flash electrically erasable programmable read only memory (EEPROM) integrated circuits.