SRAM voltage assist
The disclosure provides for an SRAM array having a plurality of wordlines and a plurality of bitlines, referred to generally as SRAM lines. The array has a plurality of cells, each cell being defined by an intersection between one of the wordlines and one of the bitlines. The SRAM array further includes voltage boost circuitry operatively coupled with the cells, the voltage boost circuitry being configured to provide an amount of voltage boost that is based on an address of a cell to be accessed and/or to provide this voltage boost on an SRAM line via capacitive charge coupling.
1. An SRAM array, comprising:
SRAM lines comprising a plurality of wordlines and a plurality of bitlines;
a plurality of cells, each cell being defined by an intersection between one of the wordlines and one of the bitlines; and
voltage boost circuitry operatively coupled with the cells, the voltage boost circuitry comprising a boost capacitor configured to provide an amount of voltage boost that is based on an address of a cell to be accessed, where the boost capacitor is coupled and decoupled to at least one SRAM line of the SRAM lines through a transistor,
where the voltage boost circuitry is configured to provide voltage boost by (i) charging an SRAM line to a pre-boosted voltage while the transistor is disabled to decouple the boost capacitor from the SRAM line; and (ii) after the charging to the pre-boosted voltage, enabling the transistor to couple the boost capacitor to the SRAM line and applying a boost command signal to a boost command terminal of the boost capacitor.
2. The SRAM array of claim 1 , where the voltage boost circuitry is configured, for a cell to be accessed, to provide an amount of voltage boost that is based on the wordline defining the cell.
3. The SRAM array of claim 1 , where the voltage boost circuitry is configured, for a cell to be accessed, to provide an amount of voltage boost that is based on the bitline defining the cell.
4. The SRAM array of claim 1 , where the voltage boost circuitry is configured to boost voltage on one or more of the SRAM lines via capacitive charge coupling.
5. The SRAM array of claim 4 , where the voltage boost circuitry is configured to provide controllable variation over the level of the boosted voltage by controlling an amount of boost capacitance used in the capacitive charge coupling.
6. The SRAM array of claim 1 , where the voltage boost circuitry is configured, responsive to a test indicating that a first portion of the SRAM array behaves differently from a second portion of the SRAM array, to provide different amounts of voltage boost to the first and second portions of the SRAM array.
7. The SRAM array of claim 1 , where the voltage boost circuitry is configured to provide an amount of voltage boost that is based on a power state of one or more of the SRAM array and circuitry making use of the SRAM array.
8. The SRAM array of claim 1 , where the voltage boost circuitry is configured to provide an amount of voltage boost that is based on measured temperature.
9. The SRAM array of claim 1 , where the voltage boost circuitry is configured to provide an amount of voltage boost that is based on measured supply voltage.
10. An SRAM array, comprising:
SRAM lines comprising a plurality of wordlines and a plurality of bitlines;
a plurality of cells, each cell being defined by an intersection between one of the wordlines and one of the bitlines; and
voltage boost circuitry coupled with the cells, the voltage boost circuitry comprising a boost capacitor configured to generate, via capacitive charge coupling, a boosted voltage on one or more of the SRAM lines, where the boost capacitor is coupled and decoupled to at least one SRAM line of the SRAM lines through a transistor,
where the voltage boost circuitry is configured to generate the boosted voltage by (i) charging an SRAM line to a pre-boosted voltage while the transistor is disabled to decouple the boost capacitor from the SRAM line, and (ii) after the charging of the SRAM line, enabling the transistor to couple the boost capacitor to the SRAM line and applying a boost command signal to a boost command terminal of the boost capacitor.
11. The SRAM array of claim 10 , where the voltage boost circuitry is configured to provide controllable variation over the level of boosted voltage from one SRAM line to another.
12. The SRAM array of claim 10 , where the voltage boost circuitry is configured to provide controllable variation over the level of the boosted voltage by controlling an amount of boost capacitance used in the capacitive charge coupling.
13. The SRAM array of claim 10 , where the boost capacitor is segmented to enable controllable variation over the amount of capacitance that is coupled to the SRAM line or lines being boosted.
14. The SRAM array of claim 10 , where the voltage boost circuitry is configured, responsive to a test indicating that a first portion of the SRAM array behaves differently from a second portion of the SRAM array, to provide different amounts of voltage boost to the first and second portions of the SRAM array.
15. The SRAM array of claim 10 , where the voltage boost circuitry is configured to provide an amount of voltage boost that is based on a power state of one or more of the SRAM array and circuitry making use of the SRAM array.
16. The SRAM array of claim 10 , where the voltage boost circuitry is configured to provide an amount of voltage boost that is based on measured temperature.
17. The SRAM array of claim 10 , where the voltage boost circuitry is configured to provide an amount of voltage boost that is based on measured supply voltage.
18. An SRAM array, comprising:
SRAM lines comprising a plurality of wordlines and a plurality of bitlines;
a plurality of cells, each cell being defined by an intersection between one of the wordlines and one of the bitlines;
voltage boost circuitry comprising a wordline boost capacitor coupled between a wordline boost command signal and a transistor, where the wordline boost capacitor is coupled and decoupled to at least one wordline of the wordlines through the transistor, the voltage boost circuitry being configured to generate a boosted voltage on one or more of the wordlines by (i) charging the wordline to a pre-boosted voltage, while the transistor is disabled to decouple the wordline boost capacitor from the at least one wordline; and (ii) after the charging of the wordline boost capacitor, enabling the transistor to couple the wordline boost capacitor to the at least one wordline and asserting the wordline boost command signal to generate the boosted voltage; and
a bitline boost capacitor having a bitline boost command terminal and a bitline terminal, the voltage boost circuitry being configured to generate a boosted voltage on one or more of the bitlines by (i) charging the bitline boost capacitor to a pre-boosted voltage at the bitline terminal, and (ii) while one or more of the bitlines is connected to the bitline terminal, and after the charging of the bitline boost capacitor, applying a bitline boost command signal to the bitline boost command terminal,
where the wordline boost capacitor, bitline boost capacitor, wordline boost command signal and bitline boost command signal are segmented to enable controllable variation over the level of wordline and bitline voltage boost.