Memory systems having a volatile memory, a non-volatile memory arranged in blocks, and a controller coupled to the volatile memory and to the non-volatile memory. The controller is configured to maintain, in the volatile memory, a list of addresses of erased blocks of the non-volatile memory. The list of addresses of erased blocks of the non-volatile memory is limited to a maximum number of list entries. The controller is further configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory in response to the list containing its maximum number of list entries and/or in response to an operation that would increase the number of list entries to a number equal to or greater than the maximum number of list entries.
1. A memory system comprising:
a volatile memory;
a non-volatile memory arranged in blocks; and
a controller coupled to the volatile memory and to the non-volatile memory, the controller configured to maintain, in the volatile memory, a list of addresses of erased blocks of the non-volatile memory;
wherein the list of addresses of erased blocks of the non-volatile memory is limited to a maximum number of list entries,
wherein the controller is further configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory in response to the list containing its maximum number of list entries.
2. The memory system of claim 1 , wherein the maximum number of list entries is a maximum number of addresses.
3. The memory system of claim 1 , wherein the maximum number of list entries is a maximum number of erased blocks.
4. The memory system of claim 3 , wherein the list of addresses of erased blocks of the non-volatile memory is limited to a maximum number of erased blocks regardless of a total number of erased blocks in the non-volatile memory.
5. The memory system of claim 1 , wherein the list of addresses of erased blocks comprises a list of addresses of blocks of the non-volatile memory upon which a block erase operation has been performed.
6. The memory system of claim 1 , wherein the list of addresses of erased blocks comprises a list of addresses of blocks of the non-volatile memory currently available for assignment to a write pointer.
7. The memory system of claim 1 , wherein the list of addresses of erased blocks comprises a list of addresses of blocks of the non-volatile memory currently available for rewriting a control structure of the memory system.
8. The memory system of claim 1 , wherein the controller is further configured to clear the list of addresses of erased blocks of the non-volatile memory after transferring the list from the volatile memory to the non-volatile memory.
9. The memory system of claim 1 , wherein the controller is further configured to initialize the list of addresses of erased blocks of the non-volatile memory from information in the non-volatile memory during initialization of the memory system.
10. The memory system of claim 1 , wherein the controller is configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory concurrently with a transfer of logical to physical mapping information from one or more additional lists in the volatile memory.
11. A memory system comprising:
a volatile memory;
a non-volatile memory arranged in blocks; and
a controller coupled to the volatile memory and to the non-volatile memory, the controller configured to maintain, in the volatile memory, a list of addresses of erased blocks of the non-volatile memory;
wherein the list of addresses of erased blocks of the non-volatile memory is limited to a maximum number of list entries,
wherein the controller is further configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory in response to an operation that would increase the number of list entries to a number equal to or greater than the maximum number of list entries.
12. The memory system of claim 11 , wherein the maximum number of list entries is a maximum number of addresses.
13. The memory system of claim 11 , wherein the maximum number of list entries is a maximum number of erased blocks.
14. The memory system of claim 13 , wherein the list of addresses of erased blocks of the non-volatile memory is limited to a maximum number of erased blocks regardless of a total number of erased blocks in the non-volatile memory.
15. The memory system of claim 11 , wherein the list of addresses of erased blocks comprises a list of addresses of blocks of the non-volatile memory upon which a block erase operation has been performed.
16. The memory system of claim 11 , wherein the list of addresses of erased blocks comprises a list of addresses of blocks of the non-volatile memory currently available for assignment to a write pointer.
17. The memory system of claim 11 , wherein the list of addresses of erased blocks comprises a list of addresses of blocks of the non-volatile memory currently available for rewriting a control structure of the memory system.
18. The memory system of claim 11 , wherein the controller is further configured to clear the list of addresses of erased blocks of the non-volatile memory after transferring the list from the volatile memory to the non-volatile memory.
19. The memory system of claim 11 , wherein the controller is further configured to initialize the list of addresses of erased blocks of the non-volatile memory from information in the non-volatile memory during initialization of the memory system.
20. The memory system of claim 11 , wherein the controller is configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory concurrently with a transfer of logical to physical mapping information from one or more additional lists in the volatile memory.