IP Library › Granted Patent US 8,874,843

Granted Patent B2

US 8,874,843 · App. 13/750,811 · Granted Oct 28, 2014

Systems with programmable heterogeneous memory controllers for main memory

Inventors: Kenneth Alan Okin (Saratoga, CA); George Moussa (Dublin, CA); Kumar Ganapathy (Los Altos, CA); Vijay Karamcheti (Los Altos, CA); Rajesh Parekh (Los Altos, CA)

Assignee: Virident Systems, Inc.

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Quick Facts

Patent No.: US 8,874,843
App. No.: 13/750,811
Granted: Oct 28, 2014
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module.

Claims (58)

1. A programmable heterogeneous memory controller, the programmable heterogeneous memory controller comprising:

a processor interface to couple to a processor;

and

one or more memory channel controllers coupled to the processor interface and to one or more respective memory channels of a main memory, each of the one or more memory channel controllers including

a memory channel interface to couple to a memory channel bus;

a common memory module controller coupled to the memory channel interface and the processor interface, the common memory module controller to generate common control signals on the memory channel bus for a plurality of differing memory modules coupled into a respective plurality of memory module sockets; and

a plurality of memory module controllers coupled to the memory channel interface and the processor interface, the plurality of memory module controllers to generate differing control signals on the memory channel bus for each of the plurality of differing memory modules coupled into the respective plurality of memory module sockets, each of the plurality of memory module controllers being programmable by a memory module software driver in response to the type of memory module coupled into the respective memory module socket.

2. The programmable heterogeneous memory controller of claim 1 , wherein the main memory is a heterogeneous main memory including

a non-volatile memory module coupled into a first memory module socket of a first memory channel bus coupled to a first memory channel controller; and

a dynamic random access memory module coupled into a second memory module socket of the first memory channel bus coupled to the first memory channel controller.

3. The programmable heterogeneous memory controller of claim 2 , wherein

a first memory module controller of the plurality of memory module controllers is programmed by a first memory module software driver to generate first control signals on the first memory channel bus for controlling the non-volatile memory module; and

a second memory module controller of the plurality of memory module controllers is programmed by a second memory module software driver to generate second control signals on the first memory channel bus for controlling the dynamic random access memory module.

4. The programmable heterogeneous memory controller of claim 3 , wherein

the common memory module controller generates common control signals on the first memory channel bus for the non-volatile memory module and the dynamic random access memory module.

5. The programmable heterogeneous memory controller of claim 1 , wherein the heterogeneous main memory further includes

a static random access memory module coupled into a third memory module socket of the first memory channel bus coupled to the first memory channel controller.

6. The programmable heterogeneous memory controller of claim 5 , wherein

a third memory module controller of the plurality of memory module controllers is programmed by a third memory module software driver to generate third control signals on the first memory channel bus for controlling the static random access memory module.

7. The programmable heterogeneous memory controller of claim 6 , wherein

the common memory module controller generates common control signals on the first memory channel bus for the non-volatile memory module, the dynamic random access memory module, and the static random access memory module.

8. The programmable heterogeneous memory controller of claim 1 , wherein

a first memory channel controller is coupled to the processor interface and to a first memory channel of the main memory; and

a second memory channel controller is coupled to the processor interface and to a second memory channel of the main memory.

9. The programmable heterogeneous memory controller of claim 8 , wherein the main memory is a heterogeneous main memory including

a first non-volatile memory module is coupled into a first memory module socket of the first memory channel bus coupled to a first memory channel controller;

a first dynamic random access memory module is coupled into a second memory module socket of the first memory channel bus coupled to the first memory channel controller;

a second non-volatile memory module is coupled into a first memory module socket of the second memory channel bus coupled to a second memory channel controller; and

a second dynamic random access memory module is coupled into a second memory module socket of the second memory channel bus coupled to the second memory channel controller.

10. The programmable heterogeneous memory controller of claim 9 , wherein

a first memory module controller of the first memory channel controller is programmed by a first memory module software driver to generate first control signals on the first memory channel bus for controlling the first non-volatile memory module;

a second memory module controller of the first memory channel controller is programmed by a second memory module software driver to generate second control signals on the first memory channel bus for controlling the first dynamic random access memory module;

a first memory module controller of the second memory channel controller is programmed by a third memory module software driver to generate first control signals on the second memory channel bus for controlling the second non-volatile memory module;

a second memory module controller of the second memory channel controller is programmed by a fourth memory module software driver to generate second control signals on the second memory channel bus for controlling the second dynamic random access memory module.

11. The programmable heterogeneous memory controller of claim 10 , wherein

a first common memory module controller of the first memory channel controller generates common control signals on the first memory channel bus for the first non-volatile memory module and the first dynamic random access memory module; and

a second common memory module controller of the second memory channel controller generates common control signals on the second memory channel bus for the second non-volatile memory module and the second dynamic random access memory module.

12. The programmable heterogeneous memory controller of claim 9 , wherein the heterogeneous main memory further includes

a first static random access memory module coupled into a third memory module socket of the first memory channel bus coupled to the first memory channel controller; and

a second static random access memory module coupled into a third memory module socket of the second memory channel bus coupled to the second memory channel controller.

13. The programmable heterogeneous memory controller of claim 12 , wherein

a third memory module controller of the first memory channel controller is programmed by a third memory module software driver to generate third control signals on the first memory channel bus for controlling the first static random access memory module;

a third memory module controller of the second memory channel controller is programmed by a fifth memory module software driver to generate third control signals on the second memory channel bus for controlling the second static random access memory module.

14. The programmable heterogeneous memory controller of claim 13 , wherein

15. The programmable heterogeneous memory controller of claim 9 , wherein

a first memory module controller of the second memory channel controller is programmed by the first memory module software driver to generate first control signals on the second memory channel bus for controlling the second non-volatile memory module; and

a second memory module controller of the second memory channel controller is programmed by the second memory module software driver to generate second control signals on the second memory channel bus for controlling the second dynamic random access memory module.

16. The programmable heterogeneous memory controller of claim 15 , wherein

Assignments (5)

RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022

From: JPMORGAN CHASE BANK, N.A.

To: WESTERN DIGITAL TECHNOLOGIES, INC.

Reel/Frame 058966/0321 →

SECURITY INTEREST Recorded Sep 29, 2020

From: WESTERN DIGITAL TECHNOLOGIES, INC.

To: JPMORGAN CHASE BANK, N.A., AS AGENT

Reel/Frame 053926/0446 →

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2020

From: VIRIDENT SYSTEMS, LLC