THERMALLY ENHANCED SEMICONDUCTOR ASSEMBLY WITH EMBEDDED SEMICONDUCTOR DEVICE AND BUILT-IN STOPPER AND METHOD OF MAKING THE SAME

1 . A method of making a thermally enhanced semiconductor assembly with an embedded device and a built-in stopper, comprising:

forming a stopper on a metal layer;

mounting a semiconductor device on the metal layer using the stopper as a placement guide for the semiconductor device that includes an active surface with a contact pad thereon and an inactive surface, wherein the active surface faces a first vertical direction, the inactive surface faces a second vertical direction opposite the first vertical direction and is attached to the metal layer, and the stopper extends from the metal layer in the first vertical direction and is located in close proximity to and laterally aligned with and laterally extends beyond peripheral edges of the semiconductor device in lateral directions orthogonal to the vertical directions;

attaching a stiffener to the metal layer, including aligning the semiconductor device and the stopper within an aperture of the stiffener;

forming a build-up circuitry that covers the stopper, the semiconductor device and the stiffener in the first vertical direction and includes a first conductive via that directly contacts the contact pad of the semiconductor device to provide an electrical connection between the semiconductor device and the build-up circuitry;

providing a plated through-hole that extends through the stiffener in the vertical directions to provide an electrical connection between the build-up circuitry and the metal layer; and

removing selected portions of the metal layer to form a thermal pad and a terminal, wherein the thermal pad extends beyond and covers the inactive surface of the semiconductor device in the second vertical direction and the terminal is spaced from the thermal pad and extends beyond the stiffener in the second vertical direction.

2 . The method of claim 1 , wherein the electrical connection between the semiconductor device and the build-up circuitry is devoid of solder.

3 . The method of claim 1 , wherein forming the stopper on the metal layer includes photolithographic process.

4 . The method of claim 1 , wherein the semiconductor device is attached to the metal layer using an adhesive that contacts and is sandwiched between the semiconductor device and the metal layer.

5 . The method of claim 4 , wherein the adhesive contacts and is coplanar with the stopper in the second vertical direction and is lower than the stopper in the first vertical direction.

6 . The method of claim 1 , wherein forming the build-up circuitry includes:

providing a first insulating layer that covers the stopper, the semiconductor device and the stiffener in the first vertical direction; then

forming a first via opening that extends through the first insulating layer and is aligned with the contact pad of the semiconductor device; and then

forming a first conductive trace that extends from the first insulating layer in the first vertical direction and extends laterally on the first insulating layer and extends through the first via opening in the second vertical direction to form the first conductive via in direct contact with the contact pad of the semiconductor device.

7 . The method of claim 6 , wherein forming the build-up circuitry includes:

forming an additional first via opening that extends through the first insulating layer and is aligned with the stiffener; and then

forming the first conductive trace that extends through the additional first via opening in the second vertical direction to form an additional first conductive via in direct contact with the stiffener.

8 . The method of claim 1 , wherein providing the plated through-hole includes:

forming a through-hole that extends through the stiffener in the vertical directions; and then

depositing a connecting layer on an inner sidewall of the through-hole.

9 . The method of claim 1 , wherein the stopper include a continuous or discontinuous strip or an array of posts.

10 . The method of claim 1 , wherein a gap in between the semiconductor device and the stopper is in a range of 0.001 to 1 mm.

11 . The method of claim 1 , wherein the stopper has a height in a range of 10 to 200 microns.

12 . The method of claim 1 , wherein the stiffener is a laminated epoxy or polyimide.

13 . A method of making a thermally enhanced semiconductor assembly with an embedded device and a built-in stopper, comprising:

forming a stopper on a metal layer;

mounting a semiconductor device on the metal layer using the stopper as a placement guide for the semiconductor device that includes an active surface with a contact pad thereon and an inactive surface, wherein the active surface faces a first vertical direction, the inactive surface faces a second vertical direction opposite the first vertical direction and is attached to the metal layer, and the stopper extends from the metal layer in the first vertical direction and is located in close proximity to and laterally aligned with and laterally extends beyond peripheral edges of the semiconductor device in lateral directions orthogonal to the vertical directions;

attaching a stiffener to the metal layer, including aligning the semiconductor device and the stopper within an aperture of the stiffener; and

forming a build-up circuitry that covers the stopper, the semiconductor device and the stiffener in the first vertical direction and includes a first conductive via that directly contacts the contact pad of the semiconductor device to provide an electrical connection between the semiconductor device and the build-up circuitry.

14 . A thermally enhanced semiconductor assembly with an embedded device and a built-in stopper, comprising:

a thermal pad;

a semiconductor device that is mounted on the thermal pad from a first vertical direction and includes an active surface with a contact pad thereon and an inactive surface, wherein the active surface faces the first vertical direction and the inactive surface faces a second vertical direction opposite the first vertical direction and is attached to the thermal pad;

the stopper that extends from the thermal pad in the first vertical direction and serves as a placement guide for the semiconductor device and is in close proximity to and laterally aligned with and laterally extends beyond peripheral edges of the semiconductor device in lateral directions orthogonal to the vertical directions;

a stiffener that includes an aperture with the semiconductor device and the stopper extending thereinto; and

a build-up circuitry that covers the stopper, the semiconductor device and the stiffener in the first vertical direction and includes a first insulating layer, a first via opening and a first conductive trace, wherein the first via opening in the first insulating layer is aligned with the contact pad of the semiconductor device, and the first conductive trace extends from the first insulating layer in the first vertical direction and extends through the first via opening in the second vertical direction and directly contacts the contact pad.

15 . The thermally enhanced semiconductor assembly of claim 14 , further comprising:

a terminal that extends beyond the stiffener in the second vertical direction and is laterally aligned with and spaced from the thermal pad; and

a plated through-hole that extends through the stiffener to provide an electrical connection between the build-up circuitry and the terminal.